Who?
Istvan Novak - senior principal engineer at Oracle
Kevin Roselle - senior staff engineer at Qualcomm
Dale Becker – chief electronics packaging engineer at IBM
Stephen Scearce– senior manager of high-speed design at Cisco
Ken Willis - product engineering director of high-speed analysis products at Cadence
What?
Our experts got together and agreed on a set of kickoff topics. These are issues that they are either currently facing or that are lurking on the horizon. The kickoff topics include:
- DC-DC converters – it’s a love - hate relationship
- AMI models for memory interfaces: single-ended signals need equalization, too
- DDR4-3200 – even the most experienced engineers can trip on this max speed interface
- System serial link compliance when utilizing multiple suppliers (chip, package, board, connector)
Interactive?
Yes!
Time will be allocated for the audience to interact with the experts.
So don't miss the opportunity to listen, learn, and get their perspective on your tough technical challenges.
Space is limited, click here to register, now!
When and Where?
Join us on August 31, 2016
Boston Marriott Burlington
Burlington, MA
Click here for agenda and details.
Speakers’ Bios
Istvan Novak
- Senior principle engineer at Oracle
- 20-plus years of experience with high-speed digital, RF, and analog circuit and system design
- Expertise:
- Signal integrity design of high-speed serial
- Parallel buses
- Design and characterization of power-distribution networks
- Packages for mid-range servers
- Fellow of IEEE for his contributions to signal-integrity and RF measurement and simulation methodologies
Kevin Roselle
- Senior staff engineer in the corporate Power and Signal Integrity Group (PSIG) at Qualcomm
- Chief technology officer at Bayside Design, Inc., a high-performance interconnect design and analysis consulting company
- Founding engineer at Chip2Chip, which later became Velio Communications, Inc. At Velio, Kevin directed work on several multi-gigabit SerDes and switch-fabric chips in packaging, PCB-level design, and channel analysis.
- Senior member of consulting staff at Cadence, where he worked on the SPECCTRAQUEST and SigXplorer tools
- Worked at Digital Equipment Corporation in several roles as signal integrity consultant and in field solver software development
- MTS at Bell Laboratories in Holmdel, NJ, where he worked on small telephone systems design
- BSEE with High Distinction from the University of Nebraska
- MSEE from the University of Michigan
Dale Becker
- Chief electronics packaging engineer for the IBM POWER and System Z Enterprise Systems
- B.E.E degree from the University of Minnesota
- M.S.E.E. from Syracuse University
- Ph.D. from the University of Illinois at Urbana Champaign
- Expertise:
- Designing the high-speed channels to enable the computer system performance and the power distribution networks for reliable operation of the ICs that make up the processor subsystem
- General chair of the IEEE EPEPS 2016 Conference and the co-chair of the 2016 IEEE EMCS embedded conference on SIPI
- Over 25 patents on electrical design of computer systems and has presented over 75 papers in refereed journals and international conferences covering many aspects of electrical computer system design, including power distribution analysis and design and modeling of signal and power distribution networks
- Member of the IBM Academy of Technology
- Fellow of IEEE
- iNEMI Technical Committee member
- Member of IMAPS and SWE
Stephen Scearce
- Sr. engineering manager in the Central Hardware Group PDS Signal Integrity team (CHG-PDS- SI) for Cisco. This team supports system and silicon high-speed design for Cisco’s ENG Routing, Wireless, Cable, and Security products.
- Expertise / primary focus areas:
- ASIC/system power integrity (DC, AC, transient)
- ASIC packaging
- SerDes design/analysis
- High-speed memory design/analysis
- Worked for Cisco for 15.5 years in the SI and EMC field
- Worked for NASA in the Electromagnetic Research Branch HIRF team
- 5 US patents
- BSET and MSEE from Old Dominion University, Norfolk VA
Ken Willis
- Product engineering director of high-speed analysis products at Cadence
- 25 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits
- Prior to Cadence, held engineering, marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity