A test point is a location within an electronic circuit that is used to either monitor the state of the circuitry or to inject test signals. Test points have two primary uses:
- During manufacturing they are used to verify that a newly assembled device is working correctly. Any equipment that fails this testing is either discarded or sent for rework.
- After sale of the device to a customer, test points may be used at a later time to repair the device if it malfunctions, or if the device needs to be re-calibrated after having components replaced
A test point can be a simple pad on a net, a through hole, or a pin where test equipment can be connected. Figure 1 shows a test point on a via.
Figure 1 - Test point on a via
The application note discussed here helps you understand the test point flow from OrCAD® Capture to Allegro® PCB Editor and vice versa. This document explains different ways of defining test points in OrCAD Capture and transferring these to Allegro PCB Editor. The application note also explains how to identify nets on which a test point is to be defined in Allegro PCB Editor.
Defining Test Points
Test points are used in PCB boards for testing signal continuity. They are added in the PCB board itself to verify the circuit or to provide test input signals. Allegro PCB Editor allows defining test points on nets, vias, and pins. However, in recent times, it has been observed that schematic engineers have expressed the need of defining test points in the front-end schematic itself. Owing to their knowledge of circuit and critical signals/nets in the design, schematic engineers wish to identify the net on which test points should be added on the PCB board.
This document discusses how you can define test points on nets in the schematic. You can take either of the following two approaches:
- Identify the nets on which a test point is to be added
- Filter off the nets on which test points are not added, allowing Allegro PCB Editor to choose all other nets for Testprep. This is done by defining the NO_TEST property.
Defining Test Points in Allegro PCB Editor
In Allegro PCB Editor you can define test points directly even if it is not defined in the schematics. A test point is generated in Allegro PCB Editor using Testprep. Testprep adds test points on nets which do not have NO_TEST property defined on them.
In Allegro PCB Editor, while using Testprep you can assign the following properties:
- NO_TEST: Attach to nets that do not require test points. In Allegro Constraint Manager, this property is specified as Prohibit.
- TESTPOINT_QUANTITY: You can limit the number of test points that will automatically be added to the net using this property.
The two properties, NO_TEST and TESTPOINT_QUANTITY, are displayed in Allegro Constraint Manager as shown in Figure 2.
Figure 2 - Allegro Constraint Manager showing test point properties
Refer to the following document for details on running Testprep:
Defining Test Points in Schematic
You can either directly define test points on nets in the schematic or identify the nets on which test points are to be added in Allegro PCB Editor.
The following sections explain the different methods of defining test points in schematic.
By adding a single pin component
Place a single pin component on the net in the schematic design on which the test point is to be defined. This single pin component can itself be treated as a test point in Allegro PCB Editor.
The footprint (PCB Editor Symbol) of this component can be a pad which will be placed on the net and work as a testpoint.
Figure 3 - Single pin component used as a test point
In the example test case, the TP_SinglePinComponent directory has a schematic and its board file, which uses a single pin component as a test point. A sample single pin component and its footprint (pad) are also present in it.
By adding property ‘NO_TEST'
As discussed above, Testprep adds test points on nets which do not have NO_TEST property defined on it.
You can identify nets on which a test point is not to be added by defining the NO_TEST property on the nets in the schematic design. To add NO_TEST in Capture, select the nets, open property editor, and click New Property to add a property with the following details:
NAME=NO_TEST
Value=YES
NO_TEST defined in schematic is transferred to Allegro PCB Editor as a net property. You can also add or delete this property from nets in Allegro PCB Editor.
Backannotating Test Point Properties to Schematic
The board designer can define or modify the NO_TEST property directly on board in Allegro PCB Editor before running Testprep to add testpoints. This information is transferred to the schematic through back annotation.
As discussed in Defining Test Points in Allegro PCB Editor , while using Testprep you can assign the following properties in Allegro PCB Editor:
- NO_TEST
- TESTPOINT_QUANTITY
- TESTPOINT_ALLOW_UNDER
- TESTPOINT_MAX_DENSITY
Among these properties, NO_TEST and TESTPOINT_QUANTITY are defined on nets and can be back annotated to the schematic. For this, make sure that the properties are set to YES in the allegro.cfg file under the [netprops] section.
TESTPOINT_ALLOW_UNDER and TESTPOINT_MAX_DENSITY cannot be back annotated to the schematic as these are defined on symbols in Allegro PCB Editor.
Refer to the app note here for the detailed step-by-step procedures on the complete flow, including a test case attached to the app note.
Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).
Naveen Konchada
Cadence Customer Support