Are you ready to simplify your workflows, tackle your design challenges with confidence, and push your projects to new heights? DesignCon 2025 is right around the corner. Join us on January 28-30 in Santa Clara, California, for our DesignCon educational sessions, panels, and booth activities.
Stop by Booth 827 for a cup of coffee and discover how Cadence can help you accelerate your PCB and advanced IC packaging design cycles with electromagnetic, electronic, and thermal system analysis, tackle advanced IC packaging and cross-platform challenges, and successfully incorporate designs with our PHY IP for LPDDR5X and Ultra Accelerator Link (UALink) IP solutions.
Cadence Sessions and Activities
The Cadence schedule at DesignCon 2025 is packed with insightful presentations by expert speakers, interactive panels, and exclusive meet-and-greet opportunities. Here’s what you don’t want to miss:
Sponsored Sessions
As usual, Cadence has a day with seven free technical sessions on Thursday, January 30, in Great America Ballroom K showcasing cutting-edge advancements in signal integrity and design strategies. Check out these two highlights:
- Industry expert Shiv Agarwal from Meta sharing insights on optimizing high-speed signal performance in the demanding environments of mixed and virtual reality applications
- Zhiping Yang, CEO of PCB Automation Inc. and adjunct professor at Missouri S&T EMC laboratory, and Cadence experts presenting a case study on how to sign off your UCIe interface, offering practical guidance on ensuring robust interface compliance in your designs.
Panels and Presentations
Cadence experts will be featured on two panels covering key topics on navigating silicon interposers with UCIe interfaces and the need for speed and sustainability for AI-driven data centers. These panels provide a unique opportunity to hear diverse perspectives from visionaries across the field.
Make sure you also learn from Cadence and industry experts during the technical track sessions:
- Presented by Cadence, Al Neves from Wild River, and Dr. Eric Bogatin from the University of Colorado-Boulder, this Wednesday session delves into the challenges of designing high-speed serial links for AI systems.
- Cadence, along with experts from Oracle, Amazon, Samtec, and ST Microelectronics, explore the complexities of power distribution network (PDN) design in a Thursday afternoon session, highlighting the need for updated target impedance methodologies that vary with frequency and spatial position.
- A Wednesday morning session showcases Cadence's innovative machine learning approach to error correction in high-speed wireline transceivers.
Booth Highlights
Special Meet and Greet - Swing by booth 827 on Wednesday, January 29 at 5:00pm to meet Dr. Eric Bogatin, dean of the Signal Integrity Academy and an Adjunct Professor at the University of Colorado, Boulder. Be one of the first 100 visitors and get an exclusive signed Rule #9 hat.
Engage in discussions with Cadence experts and get an in-depth look at our solutions, including:
- High-performance 3D electromagnetic (EM) modeling solutions for interposer, package, and PCB designs
- Advanced workflows for multi-chiplet 3D design flows
- LPDDR5X solutions at 9.6Gbps on 3nm, tailored for AI and automotive applications
- 224G Long-Reach SerDes for UALink, paving the way for next-level connectivity
- Interposer/package/PCB signal, power, and thermal integrity analysis
You’ll also gain insights into integrating real-world measurement data into EM simulations and improving designs through powerful validation techniques.
Visit our website for the complete schedule.