This week, I'm providing a very short blog. While the content is brief and simple, the positive impact to the Allegro Design Entry CIS usability is high!

The Capture INI (project level) settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial CIS database related setup. You may often need to clear out and reinitialize your Capture INI settings, but may still want to retain the CIS settings. To allow this, the 16.5 release now retains the CIS INI settings in a separate back-up file. This file retains the CIS INI settings that Capture will retrieve when it re-initializes the Capture INI settings.

As always, I look forward to your feedback.

Jerry "GenPart" Grzenia

While working on very large scale Printed Circuit Board (PCB) files that contain a huge stack-up along with thousands of footprints and numerous shapes, the performance of the  Allegro PCB Editor plays an important role in getting the board built in time. Below are example statistics for a large scale PCB:

Apart from upgrading the platform hardware to have more RAM, multi-core processor, or a better graphics adapter, there are several capabilities you can leverage in the Allegro PCB Editor that will help improve the overall performance.

Have you ever wondered how the Performance Advisor can improve the overall performance of Allegro PCB Editor when working on large board files?

Performance Advisor will analyze a design for possible performance issues and generate a report that provides solutions and recommendations to better manage your PCB design. It is an important check when working on large designs.The report generated would consist of objects responsible for performance degradation like constraints in the design that are not being used, constraint regions defined but with no values, or overlapping shapes.

In SPB 16.2, you will need to select Setup > User Preferences > Early_adopter and then select Performance Advisor to enable this function within DBDoctor.

If you are working with large scale designs and/or would like to improve the overall performance of the tool, the following Application Note should be helpful. This Application Note will cover other areas which, when tweaked appropriately, will improve the overall performance of the PCB Designs in Allegro PCB Editor.

Please click here to access the Appnote

Our Silicon Package Board (SPB) Customer Support team has initiated a new blog series promoting specific Application Notes (AppNotes) that we believe will help our customers increase their productivity in using our solutions, flows, and products.

Our Customer Support team will review new and existing Cadence Online Support published AppNotes on a periodic basis and select the “Best of the Best” for those we believe will have a large positive impact in assisting how our customers work Cadence SPB solutions. The goal is to publish a blog entry on average each month with a new AppNote for a specific SPB product area.

The first blog posted is - Customer Support Recommended – Appnote on Increasing performance in Allegro PCB Editor

Please let us know how helpful the AppNotes are by replying to each blog as it’s posted.


Jerry “GenPart” Grzenia

The 16.5 Allegro PCB Editor release contains several updates to the Graphical User Interface (GUI) to increase your efficiency and productivity in using the product.

Read on for more details...

Status Bar updates

Functional responses can be obtained by clicking fields in the status bar. For example, the field indicating the current subclass can be selected and changed to a new class/subclass. This is a good alternative to opening the Options Form over in the side panel.

Class / Subclass

In previous releases the subclass panel has reflected the active subclass of the design when the etch class is active, and has been blank in other situations. New in 16.5 is a hover prompt indicating “Active class and subclass - Click to select.” Clicking on this field produces a popup that enables you to change the active class/subclass setting from a list. In addition, the field itself will list the subclass for all classes, as well as the class name when a non-etch class is active:

Application Mode

In previous releases, the application mode provided a read-only abbreviated indication of the currently active app mode (e.g. “GEN” for General edit). In 16.5, the full application mode is spelled out and the hover prompt shows “Application Mode is <App Mode Name>. Click to select”. As with class/subclass, clicking on this field produces a selectable popup listing all available application modes. Subsequently selecting one of those will put Allegro into that application mode:

 
Super Filter

The text “Click to select” is appended to the hover prompt for this field, and clicking it will result in a selectable popup listing possible super filter values for you to assign:

Number of Selections

A new field at the far right of the status bar panel indicates how many objects are presently selected in the canvas, along with the prompt text “Number of selected objects.” This is also be a selectable field, with a popup offering you the following options previously available only within the app mode RMB “Selection set” popup:

• Clear all selections
• Select by Polygon
• (When multiple selections) Narrow select (has a pull-right to select object type for selection filtering)
• Object browser. . . (brings up the Find by Name / Property dialog)
• (When multiple selections) Select (has a pull-right to filter selection to an individual object)
• (When multiple selections) Toggle select (has a pull-right to highlight individual objects without deselecting the others)

Polygon Select Done

The polygon select command has been enhanced to automatically finish on a double LMB click. This is similar to selecting “done."

Zoom Button in Pick Dialog

A “Zoom” button has been added to the “pick dialog” to allow application mode user access to the zoom center command:

As always, I appreciate your feedback on how you're using these new 16.5 capabilites in Allegro PCB Editor.

Jerry "GenPart" Grzenia

The 16.5 Allegro PCB Router has a couple new improvements I’ll cover today – Embedded Components Support and Route Quality Improvements.

Read on for more details …


Embedded Components Support

This functionality is basically transparent to the Allegro flow designer. The Router will just translate and route these components normally. For standalone users of the Allegro PCB Router, a new syntax has been added to support via keepouts that are required by embedded components for proper routing. For standalone users, changes have been made to add keepouts needed for embedded components.

Routing:

Proper fanouts should be completed before using the Router to ensure access to other layers. The fanouts for embedded components can go up or down as parts are no longer top/bottom mounted. If embedded devices are placed on plane layers, the router can't access pins on these layers. Also, the Allegro PCB Router can't terminate a via on a plane layer ,so fanout routines cannot do via-in-pad at these locations. So, the recommendation is to NOT place embedded components on plane layers.

Route Quality improvements

The Allegro PCB Router has focused on the quality of differential pair routing in particular.

Differential pair routing:

The routing engine has been enhanced to consider differential pair objects as a single entity and avoid the splitting of the differential pair. This will especially help when the differential pair is entering a regular pin array or BGA.

New Cost has been added to control the differential pair routing. This will allow designers to control the routing of differential pair when the differential pairs may split:

    cost dp_push_squeeze [free|forbidden|[0-100]]

[free]    Diffpair can be squeezed to produce uncouple violation (actual gap < gap-tolerance-) if required to produce DRC-free layout. actual gap < min_line_spacing is not allowed, and push is considered as failed.

[forbidden] Diffpair after push should maintain exact primary/neck gap; any squeeze is illegal.

However, Setting the value to forbidden may increase delay failures.

Post Routing Diff Pair Clean up improvements:

Enhancements have been made in post route geometry clean up for differential pairs. The improvements include, but are not limited to cleaning up staired patterns, removing bends, cleaning uncouple bumps and reliability improvements.
This further enhances the router's ability to provide good diff pair solutions. There are no additional controls or commands needed for these improvements. The "Clean" and "Critic" commands have been enhanced to incorporate these changes.

Please share your experiences using these new 16.5 capabilities.

Jerry "GenPart" Grzenia

The 16.5 Allegro Package Design (APD) product has been modified to provide a different type of method to control wire bond settings for groups. It is important to note the differences between these new group settings and the wire bond groups that existed prior to 16.5. In these prior releases, a wire bond had to strictly adhere to a wire bond group, whereby the group defined the characteristics of the wire bond. In contrast, no group settings need to be tagged to wire bonds. They are optional and simply a means to quickly assign characteristics to a set of wire bonds without being attached to them. They are more extensible since the designer can define one or more attributes instead of a specific number of wire bond attributes. Also, they can be re-used from design to design.

Read on for more details …

This feature provides an alternative manner for setting up wire bonds in the design. If the designer wishes to use this capability, the recommendation is that they follow this flow:
1.     During design initialization, load the file of pre-defined wire bond settings groups.
2.     During wire bonding, select the settings group that applies to the fingers being added or modified. If items from multiple settings groups are being modified, do not select a settings group.
3.     If new settings groups are added or existing groups modified at the end of the design cycle, export these for use in future designs.

The most common use model here will be to load an existing set of settings groups from a pre-defined XML file. To do this, open the settings groups form and browse to the master definitions file. Alternatively, the designer will enter this form and manually define the settings groups. When finished, they will most likely save this out to disk for later reuse across similar designs.

When performing wire bonding, the designer can select a settings group from the pull-down list of defined groups to apply that group’s configuration to the ministatus panel and, thus, any objects currently selected for manipulation.

Menu and Command-Line Access

This feature does not exist as a standalone command. It is available through the Route > Wire bond > Settings (or RMB > Settings if in a wire bond command already) command.  

The screenshot below illustrates the user interface for creating, importing, and exporting wire bond setting group definitions. This is available via a new button on the main Route > Wire bond > Settings form (see the second screenshot below):

 
•       Active Group: This is the group that is currently under edit in the “Definition” section lower in the form. Defaults to the first group alphabetically if there are groups defined for the current drawing.
•       Add: Press to add a new settings group definition.
•       Copy: Press to copy the current settings to create a new group definition based on it (will also require a group name, just like add).
•       Delete: Press to remove the active group definition from the database.
•       Master Definitions: This pull-down will allow the user to select from any standard group definition files found in their techpath (works the same as the wire profiles master definitions pull-down). Alternatively, the designer can select the “Browse…” entry to browse to any available file on disk, or the Clear option to disassociate with the master definitions file.
•       Save…: Save the set of group definitions from this database to an external XML formatted file for reuse in other designs.
•       Refresh from Master: Press this button to refresh the definition of the active from the master definitions file. Again, it works similarly to the profile definitions form button of the same name.
•       Checkboxes beside fields in the “Definition” area of the form: When one of these checkboxes is checked, that field will be configured when the active group is selected. If unselected, the existing value for this field will be left unchanged when this group is selected.
•       Value fields in the “Definition” area of the form: If the checkbox beside a field is enabled, then the value field will be configurable. The selectable / enterable values for the fields are exactly the same as those you would be able to select / enter for the corresponding field of the wire bond add, move, or change characteristics form. For example, the “Bubble” field has options of “Shove All”, “Shove Path”, and “Shove Off”.

Here is a screenshot showing the new button for accessing the pre-defined wire bond group settings:

 

Finally, when you're in one of the wire bond adding / editing commands, such as changing characteristics, there is a new field in which you can select a pre-defined settings group to configure fields on the form. One illustration of the form is shown below for the Add Wire bond command. Whenever the Add Command is invoked, this field is blank. The designer can select any existing pre-defined group settings in the database. If a group is selected, the attributes of that group are reflected on the other fields on the form. For example - if group “JM_FING_GRP” defines an “Align with Wire” alignment, the current Alignment value with be changed to “Align with Wire”:

 
As always, I look forward to your feeback!

Jerry “GenPart” Grzenia

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin connection) is a common requirement in the PCB design. The separate force (F) and sense (S) connection at the load eliminates any errors resulting from voltage drops in the force lead. The Kelvin Sense connection is routed by separating the sensing signals (S) from the lines, and delivering the power to the load (F). This type of connection prevents noise related problems in a closed loop system because it allows for more accurate measurement of the sense voltage at the load.

Consider the following figure:

A long resistive PCB trace is still used to drive the input of a high resolution Analog-Digital Converter (ADC), with low input impedance. In this case, however, the voltage drop in the signal lead does not give rise to an error, as feedback is taken directly from the input pin of the ADC and returned to the driving source. This scheme allows full accuracy to be achieved in the signal presented to the ADC, despite any voltage drop across the signal trace.

The requirement is to implement this at the schematic created using Allegro Design Entry HDL (DEHDL) to drive the PCB board created using Allegro PCB Editor so that both Force and Sense signals can be identified and constrained independently, and still allowed to be physically shorted in layout.

Flow Overview

This flow is based on a special logical symbol, which is created and saved in a library. The force sense library symbol(s) has shorting schemes defined within the symbol definition, which allows the engineer to seamlessly define the nets to be force sense. When placed in a schematic, the shorting scheme will short at least two sense lines to a force line. While packaging the schematic, separate nets are generated for the Sense and Force lines which are passed on to the PCB board file. As shown in the image below, four sense lines are connected to a force line using the library symbol. Inside PCB Editor, a symbol gets placed, and defines the location of the short for force and sense signals.

The pins of the schematic symbol will have a unique property called PIN_SHORT whose value consists of the logical pin names. While packaging the schematic (running File > Export Physical), based on the <project>.CPM directive, the Packager-XL(PXL) acknowledges the PIN_SHORT property value and creates a NET_SHORT property with the value containing the physical net names connected to the logical pin names.

When you look at the PCB Editor DRA symbol for the footprint, you will see that the pins with different pad stacks are placed at the same location.

Constraint Assignment

This flow allows for individual net constraints to be assigned and used in the front to back flow. As an example, Max Propagation Delay and trace width can be defined.

Refer the following AppNote for the detailed procedure used to implement the Force-Sense (Kelvin) connection using Allegro Design Entry HDL (DEHDL) & Allegro PCB Editor.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Cadence Customer Support

The 16.5 PCB SI product’s rectangular mesh scheme is used for shapes, cutouts, slots, anti-pads and voids within shapes. The mesh cell size you pre-specify is the maximum cell size ,and the system will automatically adjust/reduce the cell size if necessary. You can ignore the meshing for anti-pads and small shapes/voids through the Preferences settings.

Read on for more details …

Analyze Menu

All analysis functionality is available on the main PDN Analysis GUI:

 

In the mesh dialog, there is a brief description for meshing and all functions:

 

Preferences

Selecting the Preferences button brings up the Preferences form:

 

The General tab sets many of the default values. The Simulation tab sets the frequency range and maximum number of points for frequency-domain analysis, duration time, and time step for time-domain analysis. The top section of the Field Solver tab contains the settings for mesh generation:

 

The Mesh settings are one area of settings where a tradeoff between accuracy and performance is set. The default settings are for a Regular mesh with all voids in shapes included in the mesh. If you select the Ignore option from the following drop-down list, then all anti-pads of vias/pins will be ignored during the meshing. If you select the Include option, then all anti-pads of vias/pins will be meshed exactly:

 

You can ignore small island shapes or small voids by specifying a value for Ignore all shapes/voids less than:

    


This value is a scale factor of the maximum mesh cell size you specified (fine, regular or coarse or custom size).
Start the mesh by selecting the Mesh button on the Power/Ground Plane Meshing form:

 

Once the meshing is started, you will see a progress dialog appear and then the PDN Audit Results:

 


Mesh Results

Depending on your layer settings or specific design configuration, you may not see any mesh displayed in your design:

 
To aid in reviewing any PDN results including mesh generation, it is recommended that you pin the Options and Visibility fold out window panes in the PCB SI canvas:

 

The Options panel displays the type of analysis run and allows you to cross probe to the canvas and select the layer to review. Use the Review pull-down in the Options panel to review a specific layer of interest in the design. Select the mesh in the canvas to see the net name appear in the Options panel:

 

Please share your experiences using this new 16.5 capability.

Jerry "GenPart" Grzenia

The current Allegro Design Entry HDL (DEHDL) Page Search toolbar works only on the currently opened schematic page. If the scope of the search is different from the current page, then the Advanced Find & Navigate functionality can be used. This new feature also allows you to define the objects which you would like to search for the text.

Read on for more details …

The Find Filter (available from the Page Search toolbar) has a separate User Interface and acts as a selection filter for objects which can be used in various operations including search. This feature allows you to define the scope of a search and you can search for components, nets, properties, notes, images, pins, and plumbing bodies. You can search by using regular expressions, wild cards, property names and values. You can use the Find dialog box which can be launched by clicking on the  button in the Page Search toolbar or using the short cut key Ctrl + F


 

This opens the Advanced Find dialog box:

 
Filter Options -
The check boxes allow you to control the objects to be searched.

Find What -
Use this to enter a search query string. In case of Components and Nets, you can also specify the Property Name Value pair as search criteria using the [>>] Button. The property name and value that you type in this window is automatically updated in the Find What combo box.

For example:
Property Name: FOO and property value: BAR; will be displayed as %prop('FOO','BAR')% in the combo box.

This combo box supports:
Directly typing into the search query string
Previous search query strings are listed in the dropdown list in the current session
Copy and Paste

Look in -
This field defines the search scope - complete design, the current page, or the current schematic selection. Once all the fields have been specified, clicking the Find All button executes the search operation.
 
The search results are displayed in a dockable Search Results window:

 
The Search Results window contains standard window type columns displaying the:

• Design Name
• Physical Page Number
• Result Object Type
• Object Details
• Property Name
• Property Value

The different rows display the search results. When you double-click one of the rows, it will navigate and zoom in to display the object. You can select the contents of this window and copy them to the clipboard to paste in a text file or Excel worksheet. This window also displays the number of results found and the time taken to search them.

Steps to search any text from the Advanced Find and Navigation Window:

1. In the Page Search toolbar, click on the    button to launch the Advance Find dialog box.  

2. Specify the Filter Options to define the objects on which the text needs to be searched.
3. Specify the text to be searched.
4. Specify the search scope.
5. Click on the Find All button to run the search.
6. The search is launched based on the selections made in the dialog box and the results
are displayed in the docking window.
7. In the docking window, you can:
     a. Sort the results
     b. Filter the results
     c. Double click on a row to navigate to the object.


To find any text on the page use the find text box in toolbar.

 

As always - I look forward to your feedback experiencing this new 16.5 capability.

Jerry "GenPart" Grzenia

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide a more flexible and robust designer experience. It can now be launched in a stand-alone mode, is faster in launching, can open multiple flows, and you can customize it by adding new buttons!

Read on for more details …

Here’s a screenshot of the new Flow Manager:

You can open the last project, and select from a list of last used design or library projects:

There are project type icons show in the list:

Tabs are available to indicate multiple open projects:

Message Manager

A new messaging system is available to communicate at the company, site, or team levels. The Administrator can construct/edit/view all messages, and all others can view messages. These messages are all viewed from within the Flow Manager. When a new message arrives, the message button will highlight and you can view the new message:

Here are all the options (from sorting, selecting message has been read, etc.) available:

Here are the authoring options available for the Administrator:

Flow Manager New Features

You can now track your progress of steps through the flow:
–    Completing a step automatically moves focus to next step
–    Step status automatically set to “inprogress” when an activity is detected (button pushed or checklist unchecked)
–    Step is automatically marked complete when checklist is complete
–    Checklists can be order-dependent (if one checklist item is unchecked – all remaining items uncheck)

As always, please share your experiences in utilizing these new capabilities.

Jerry “GenPart” Grzenia

Starting with release 16.5, it is possible to export data from Allegro PCB Editor into PDF files. PDF files are more portable and secure in comparison to .brd files and can be used by customers to share a subset of design data with their vendors who do not need direct access to design data. PDF files can easily be posted on websites and opened within browsers.

Read on for more details …

Basic Information

The PDF output is driven by Artwork Film Records.  It also exports net and component data along with properties. If you try to export all the data, the file size becomes larger than the board file.

• The PDF files generated can be viewed in Adobe Reader 9.0 and Adobe Reader X.
• The utility can be run from the command line as well as the Allegro PCB Editor UI.

Here’s what the PDF Publisher form contains:

 

PDF Generation

The PDF generation is based on the Artwork films defined. Each film becomes one sheet of the PDF file. There are many control options available in the PDF generation.

Some of these key options are:

Security
There is a separate password for opening the file -- and another for modifying the permissions.  The permissions are listed under File > Properties in the Adobe Reader.  The permissions can be changed in Adobe Acrobat (if it is not protected with a password).

Board/Symbol Outlines
If  this is option is set, the board and symbol outlines are added to all layers if the PIN CLASS is exported in the film.

Filled Pads, Filled Shapes, Drill holes
Can be turned on and off.

Property Data
Property data can be made made visible in Adobe Reader's model property dialog (the lowest part of the model tree). Property data consumes a lot of space.  It needs to be added judiciously.  You can control which properties are added to the PDF file in the Property Parameters tab.

Test Point
You can generate test point information in the PDF file and it will be available in the PDF output model tree.

Automation
The PDF file can be generated directly from a batch command.

Here’s a screenshot of the various Layers and Model Tree objects available in the PDF output:

 
As always – I look forward to your feedback in using this great new capability.

Jerry “GenPart” Grzenia

In the Allegro PCB SI 16.5 release, static IR drop analysis has been integrated into PDN (power delivery network) analysis, with several new features added, such as current density display and the display of current direction.

Read on for more details …

Analyze Menu

To invoke Static IR Drop analyze, select Analyze > Static IRDrop Analysis at the bottom of the PDN Analysis form:

 

This will open the following window:

 

Field Solver Preferences

If you select the Preferences button and select the Field Solver tab, you can see the field solver options in the bottom section:

In this tab, you can select to use the full wave model (for high frequencies) or equivalent circuit (for low frequencies) since this option does not affect static IR drop analysis (Static IR drop will calculate the resistor with equations based on the mesh). You can ignore some layers which will ignore all shapes of the specified layers during the modeling. The ambient temperature will be used for static IR drop analysis and PI analysis, the surface roughness is used for PI analysis, and the debye model can be used for future model extraction.

Saving Analysis Results

By default, the analysis results will be saved using the .brd file name with different extensions. If you want to run multiple simulations for the same board file with different settings, you can change the session name for each simulation to store the results. Otherwise, the previous results will be overwritten by the new analysis. Select the Session button in the Static IRDrop Analysis dialog. This will open the Session Name dialog:

 

Display Options

The Options pane in Allegro PCB SI contains information specific to IRDrop analysis:

 

The default layer to Review is Top. This layer may or may not have any shapes on it for the DC Nets that are being analyzed. Use the Review pulldown in the Options pane to select a specific layer in the design:

 

The color contour that appears depends on several factors: the actual analysis results, the threshold values set in the main dialog, and the Color Legend.
Selecting a point on a net that was analyzed will display the value at that location in the Options pane:

 

To see the display options for static IR drop, right click in the PCB SI canvas to see the menu:

 
The Set reference command allows you to pick a reference point in the design which will be graphically displayed on the canvas. Subsequent probe points will be displayed in the Options pane with the actual drop value at that point and the relative voltage value to the Reference point. In the Options pane, select the Color Legend radio button, and you will see the following:

 

In previous releases, this legend was fixed. To change the color legend, select the Custom button in the Options pane to open the Color Legend dialog:

 

You can set different color legends for different result (current, voltage, impedance, density, and temperature rise) by selecting the Format pulldown and the Method options. Use the RMB menu to select the other Display options for IRDrop analysis - Display Mesh, Display Current, Display Density, and Display TempRise. If you are just running IR Drop, it is not necessary to run the Mesh analysis separately. The mesh that was generated for IR Drop can be accessed using RMB > Display Mesh. If you RMB select 3D EMViewer, the 3D result will be displayed in the 3D EMViewer:

Please share your experiences with this new 16.5 capability.

Jerry "GenPart" Grzenia

Prior to the 16.5 release, the search capabilities in Allegro Design Entry HDL (DEHDL) have been quite limited. This has changed in the 16.5 release with the introduction of a new toolbar for page level search and an Advanced Search and Navigate functionality.
 
Read on for more details …

The Page Search option enables you to search for text on the current page. The text can be a symbol text, net name, property or part of a note:

 

The result is displayed in a docking window which can be docked on any side of the DEHDL window.
 
The Search Results window contains default columns displaying:
a. Design Name
b. Physical Page Number
c. Object Type
d. Object Name with Path Property for Components
e. Property Name
f. Property Value

The result rows display the different objects on which text has been found. When you double click one of the rows, it will navigate and zoom in to display the object. You can select the contents of the window and copy them to the clipboard to paste in a text file or Excel worksheet. This window also displays the number of results found and the time taken to search them.
 
Detailed steps to search the text on the current page:
 
1. In the Page Search toolbar, specify the text to be searched and press ‘Enter’ key.
2. The current page is searched for the text and the results are displayed in the docking window.
3. In the docking window, you can:
    a. Sort the results
    b. Filter the results
    c. Double click on a row to navigate to the object.

I look forward to your feedback!

Jerry “GenPart” Grzenia

A recently published AppNote on converting a PADS ASCII file to Allegro PCB Editor has eased the life of many users by providing a step-by-step methodology and appropriate debugging techniques. It also covers various scenarios where Allegro PCB Editor generates errors or warnings during the translation, and explains how to debug errors and obtain a neat board file (.BRD) to be used in Allegro PCB Editor.

The PADS translator can be launched from File > Import > CAD Translators > PADS, from within Allegro PCB Editor. This translator converts the PADS database files (.asc) into Allegro PCB Editor board database files (.brd). It is assumed that the PADS database being translated is completely placed and routed.

Prerequisites for running the translator

• PADS ASCII file. (.asc)

PADS Layout creates an ASCII database version file (.asc), which contains all information about decal, part type, part, signal (logical connectivity), route (physical connectivity), and graphics.The component mapping from PADS ASCII file to Allegro prototypes is as per the table given below:

• Options file (.ini)

This is the PADS to Allegro PCB Editor Layer mapping file. The accuracy of the translated Allegro PCB Editor .brd file depends on the accuracy of the Copper layer mapping in the layer mapping file (Options File). The default pads_in.ini file is located at <Cadence_Install_Folder>/tools/pcb/bin location. It is advised to have a copy of the default pads_in.ini file in the work area and modify it accordingly.

Steps involved in the translation

1. Create a PADS ASCII file from the PADS job file (.pcb).

2. Create an options file and map the PADS and Allegro PCB Editor layers.

3. Execute the translator.

4. If there are any errors, the translation fails. Open the pads_in.log file to view the errors.

5. Correct the errors either in the .asc or .ini files. At times you may need to recreate the .asc file.

6. Re-run the translator.

7. Open the translated .brd file and review all aspects (pad geometries, symbol geometries, stackup, shapes, and so on) of the design for completeness and correctness.

Note that the translator does not guarantee 100% translation of everything. You need to edit the design that can be maintained completely within Allegro PCB Editor.

The pads_in application reads the input file and determines the number of etch/conductor layers it uses. If all required program arguments are not specified, the translation Options dialog box appears as follows:

The window above allows the users to modify the pads_in.ini file before translation begins.

Avoid editing the default pads_in.ini file located at <Cadence_Install_Folder>/tools/pcb/bin, instead, make a copy of the pads_in.ini file in the working folder and modify the same.

The PADS to Allegro Layer Mapping fields defines the element-layer mapping. The list box contains all the PADS objects (Lines, Copper, Text, Decals, Pads and Vias) and the name of the class and subclass to be mapped with in Allegro PCB Editor. Although the default mapping is done according to the pads (.asc) file, users can map the class / subclass name if needed. Each element appears once for each PADS layer, for a total of 31 entries per element.

All 2D lines on PADS layer 0 are mapped to the BOARD/SUBSTRATE GEOMETRY class and the subclass ALL, which is not pre-defined. Lines on PADS layer 1 map to the ETCH/CONDUCTOR class and the subclass TOP/SURFACE and so on. The translator presets all-necessary ETCH/CONDUCTOR class mappings by default, even if a previous translation created the options file. This is also true during batch translations.

Files Generated during translation

The following files are generated in the output directory after translation is complete:

Most of these are temporary files generated for use by the translator. They remain in the output directory only for reference. The key file is the Allegro PCB Editor board (.brd) file, which is the output from the translation.

Refer to the complete AppNote for a detailed procedure about each of the steps involved in the translation and about the known problems and solutions.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

The 16.5 Allegro Design Workbench (ADW) now supports multiple shopping lists.

In a nutshell, multiple shopping lists support these capabilities:

•    Provide viewing multiple lists from:
–    One or more common list directories
–    One or more other project directories
–    One or more specific files
–    Lists created from an outside source in the proper format can be referenced

•    Functions for:
–    Adding part to schematic
–    Adding part to current project shopping cart
–    Show details

•    Library Validation:
–    Verifies all entries are in reference library
–    Displays all messages and icons according to part status

•    Configuration:
–    Manual entry into .cpm file ( project.cpm or site.cpm)
–    GUI Based path/file configuration in CB

As always, I look forward to your feedback!

Jerry “GenPart” Grzenia

The 16.5 Allegro PCB Editor now has the added ability to accentuate objects and layers in Allegro PCB Editor by providing pattern support.

Read on for more details …

Stipple pattern support is provided through the assign color, highlight and color commands. The assign color command allows you to assign custom stipple patterns to objects in addition to assigning the color and default highlight patterns it currently supports.

The highlight command allows the assignment of a stipple pattern to objects only. No color assignment is done. This is the main difference between the highlight command and the assign color command. The find filter options for this command are the same as the assign color command. In order for stipples to be seen you must not have the variable "display_nohilitefont" enabled:

 

The Color dialog has been enhanced to allow stipple pattern assignment to layers. Assigning a pattern to a color cell is applied to all corresponding objects on that layer:

 

Assign Color command

Stipple patterns have been added to the Options form associated with the “Assign Color” command. A pull down is also provided to enable or disable pattern assignment. The pull down states are -
•    Solid
•    Selected Pattern - The selected color and pattern are assigned to objects. Selected pattern is displayed in ‘Selected pattern’ button.

The first pattern is the standard default "candy cane" stripe that was used in previous versions of Allegro PCB Editor:

 
Highlight command

This command assigns stipple patterns to objects without affecting the object color. A stipple pattern can be selected from the pattern buttons in the Options form. Selecting the first button deselects the active pattern.

Highlighting fixed elements

A new color dialog enhancement helps identify fixed objects by stipple pattern overlays. Assign any one of the available 15 stipple patterns to the new Fixed Object entry located in the Display folder of the dialog:

 
Check out the movie !

As always, I look forward to your feedback on this new 16.5 capability.

Jerry “GenPart” Grzenia

The SPB 16.6 Release is available! You can download it from the Cadence Software downloads site.

Here are just a few press announcements on the 16.6 release –

New Allegro 16.6 Release Accelerates Timing Closure on High-Speed PCB Interfaces by 30 to 50 Percent

Announcing OrCAD 16.6—A One-Two Punch for Mainstream PCB Engineers

Cadence Allegro Accelerates Product Creation Through Efficient Collaborative ECAD Environment Using Microsoft SharePoint

Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

What’s New in Cadence OrCAD 16.6 Release  

Cadence Releases OrCAD 16.6, Boosts PSpice Performance By Up to 20 Percent



I’ll be blogging about some of the most helpful product features over the coming months, but here are just some of the new 16.6 capabilities that will increase your design productivity…

Allegro PCB Editor

• Support for embedding components with dual-sided contacts and vertical components on the inner layers of a PCB
• New embedded cavity DRCs
• Faster timing closure with auto-interactive route delay tuning (AiDT)
• PCB Team Design Option accelerates design implementation
• Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
• Offset routing allows users to route off-orthogonal angles to avoid coupling high-speed signals with substrate glass fiber-weaves
• New Slide function
• Export / Import design data to and from manufacturing using the open industry-standard IPC-2581
• New artwork control form allows users to assign film record classes and subclasses to a film record
• General Edit Application Mode allows users to assign a single region constraint to multiple region shapes
• Align components by edge (top, center, bottom) using DFA constraints or equal spacing (controllable by user-defined equal spacing and + and - buttons)
• Support for text in Place Replicate
• Quickplace allows component overlap (user-defined % overlap) to get the components on the board faster
• Refresh a symbol by instance
• New command allows users to add rectangles with parameterized corners (champhered, rounded, or orthogonal)
• Dynamic shape allows thermal width for cross-hatch shapes based on the cross-hatch line width
• New display option overlays net names along cline path, pins, shapes, and flow lines
• Lines and text can now be moved outside their present class-subclass structure
• Select objects by “Lasso” or “path”
• Highlight or de-highlight nets associated with a component
• DRC can now be run “by window” when online DRC is turned off
• Specify any text for the associative dimension value using the optional Text filed in the Options tab
• Specify separate output files for plated versus non-plated (NC) routing
• Pastemask-to-pastemask DRC will check the “Package Geometry - Pastemask_Top” shapes within the same symbol
• and more …

Allegro Package Designer

• Shape Shorting - Via Array
• Bondwire Text In
• Wirebond Application Mode
• Assembly Design Rule Check (ADRC)
• Open Cavities
• Geometry to Symbol
• and more …

Allegro PCB SI

• Setup/Audit Enhancements
• SigXP Via Enhancements
• Auto-solving Models in SigXP
• Channel Analysis Enhancements
• PDN Enhancements
• PDN DeCap Management
• and more …

Allegro RF SiP

• Library Manager Flow Improvements
• Support for curves in RF Shape Routing
• Bond Wire Retain Flow
• and more …

Allegro RF PCB

• Improvements to importing from Agilent ADS to Allegro Design Authoring
• Support for new ADS RF etch elements libraries
• Snap improvements
• “Add Connect” allows users to connect to the edge of a pad, or overlapping a pad
• Scaled copy allows snap to pad edge
• Unnecessary DRC errors removed when netlist is imported into Allegro PCB Editor
• Via exchange between ADS and Allegro environment
• and more …

Allegro Design Entry HDL

• Interface Aware Design (Netgroups)
• Split hierarchical symbols and support for hierarchical nets in the Cross Referencer enable team design on designs with large pin-count components like microprocessors
• Constraint comparison utility allows users to compare constraints from two HDL schematics, PCB designs (brd), modules, and constraint files (dcf)
• Enhanced object filtering and visibility in the Constraint Manager, plus an option to use higher level net names for Xnet naming
• and more …

Allegro FPGA System Planner

• Support for additional FPGA architectures from Actel (ProASIC3), Altera (Cyclone V, Stratix V), and Xilinx (Virtex 7)
• Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
• Support for new termination schemes
• Design Compare
  and more …

Allegro Design Workbench

• Team Design Authoring solution now provides work-in-progress design data management and an efficient collaboration environment using SharePoint 2010
• Comprehensive library model management for logical schematic blocks and physical modules
• Configuration Manager Enhancements
• Design Migration Enhancements
• Flow Manager Enhancements
• and more …

Allegro Design Entry CIS

• OrCAD Schematic – Signal Integrity Flow
• Enhanced Save Function for Design and Library
• Enhancements in the Find Function
• Enhancements in Cache Updates
• Project Save As Enhancements
• NetGroup Enhancements
• Design Level Auto-RefDes
• Locking Reference and Designator Properties
• Design Rule Check (DRC) Enhancements
• Full RefDes support
• CIS – Link Database Part
• and more …

Allegro AMS Simulator

• Advanced Options
• Probe DAT Version Upgrade - 64-Bit Data Precision
• Undo Support for Capture Netlists
• Enhanced IBIS Support
• Multi-Core Engine Support
• Configuring Menus and Toolbars
• Encryption Enhancements
• New Models
• and more …

As always, I’ll look forward to your feedback on how you’re using these new 16.6 capabilities!

Jerry “GenPart” Grzenia

The Component Alignment feature is available in Placement Edit Application mode. It was introduced in the Allegro PCB Editor 16.3 release and now enhanced in 16.6 to support the following new options:

• Alignment Edge
  • When aligning vertically, select ‘left’ or ‘right’ as the edge to base the alignment on
  • When aligning horizontally, select ‘top’ or ‘bottom’ as the edge to base alignment on
• Spacing Options
  • Use DFA Constraints - Compress components in the selection set to their minimum DFA clearances.
  • Equal Spacing - Algorithm computes space between the first and last component of the selection set then divides by the number of components resulting in an equalized spacing gap between each component. Use the increment/decrement controls to adjust component spacing real time.

Read on for more details…

When you window-select a group of components you can hover over the anchor component and select RMB – Align Components. The Options Panel for Alignment controls include -

• Alignment Direction – Horizontal or Vertical
• Alignment Edge – Bottom, Center, Top or Left, Center, Right
• Spacing – Off, DFA, Equal

 


Here’s an example showing ‘Alignment Edge’ to ‘Top’. The alignment is based on the place-bound shapes of each symbol:

 

Here’s an example showing ‘Use DFA constraints’. This effectively compresses the selection set to the Minimum DFA clearance rule between each of the components:

 


In the following example, we've done a window-select of 3 connectors, then selected RMB – Align Components -

• Select the ‘Equal spacing’ – The computed space between each connector in this example is 123.50 mils.
• Use the ‘+’ option to increment the space (value of your choice)
• Use the ‘-’ to decrement the space

Here's an example showing that in the value field adjacent to the decrement and increment buttons, you can enter specific values (in this example - 25 mils). You can click on the ‘+’ and ‘–’ buttons  to decrement/increment the spacing gap by the specified value you entered:

I look forward to your feedback!

Jerry "GenPart" Grzenia

In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with any routing on layers between the two shapes.

The 16.6 Allegro Package Designer (APD) product now provides a mechanism for constructing these arrays of shape-to-shape shorting via arrays, deleting them, and updating them as the design progresses.

Read on for more details …

You first select the two shapes to be shorted together. This will update the form fields to restrict the padstacks available, and, if parameters already exist for this shape pairing, will optionally load the existing via array values. You can customize any fields as necessary on the form, and finally presses the “Add Vias” or “Remove Vias” button to perform the desired operation.

Note:  If the two selected shapes already have a via array between them, it will be cleared before generating a new array.

Manufacture > Shape Via Shorting:

The RMB popup menu, shown below, contains the standard Done, Oops, and Cancel items.
As well as entries for add vias and for remove vias:

• Padstack: This will list only those via padstacks applicable for the currently selected shapes. For instance, when the command is first started (no shapes selected), it will show all via padstacks in the design. When you select the first shape, the list gets trimmed to just those that start or end on the specified layer. When the second shape is selected, it is fully restricted to only those padstacks going between those two specific layers. At any time, if the current selection becomes invalid for the selected shapes, the tool will change to the first padstack alphabetically.  
• Spacing: The airgap between vias in the via array. This is derived from the current selected via padstack and pitch. You should ensure this value is at least equal to your via to via DRC constraint value for the constraint set this net belongs to.  This defaults to the via to via DRC spacing constraint on the top layer of the design.
• Pitch: The center to center distance between vias in the shorting via array. This is tied to the spacing value above, and changing one will change the other.
• Array Angle: The angle at which the array will be created. A 0-degree angle means all the vias are placed in horizontal rows / vertical columns like a standard grid. Adding an array angle is useful is the shape is primarily at an angle (think like the spokes of a wheel). The default value will be 0 degrees.
• Rotate Vias at Array Angle: If you specify an angle for the array above, and the padstack definition consists of any non-circular pads, drill holes, etc., you may wish to have the vias instantiated with a rotation that matches the array angle to maintain consistent separation. This option allows you to do that.
• Starting Position: Where the reference point for the via array is. Choices are upper left/right, lower left/right, and custom point. The corner selections are relative to the reference shape’s extents box.
• Offset X / Y: The offset X and Y values relative to the indicated starting position. For example, an X offset of 50um from the upper left corner will have a “legal” via array position 50 microns to the right of the top-left corner of the reference shape’s extents box. The array will extend from this point in all directions, at the pitch and angle specified, to cover the entire shape region.
• Custom Point X/Y: If the starting position is “Custom Point”, these fields are enabled, and allow you to specify an absolute database position to use as the via array’s reference position. This is particularly useful if one needs to offset via arrays between different layer pairings, or if multiple via arrays connect to a single plane shape.
• Use DRC Constraint Values: If enabled, this will cause the tool to pull the required spacing constraints from the DRC constraint system for the database. Thus, different values can be had on each internal layer, on each shape’s layer, and in constraint regions. Defaults to on.
• Via to Shape Boundary: If not using the DRC system’s constraint values, you may enter a value for the vias to clear the two shorted plane shapes’ outlines. This defaults to the via to shape spacing on the top layer of the design if enabled.
• Via to Conductor (Shape Layers): If not using the DRC system’s constraint values, you may enter a value for the vias to clear other routing objects (pins, vias, clines, etc) on the same layers as the shapes being connected. This defaults to the via to cline spacing on the top layer of the design if enabled.
• Via to Conductor (Internal Layers): If not using the DRC system’s constraint values, you may enter a value for the vias to clear routing objects (pins, vias, clines, shapes, etc) on all routing layers BETWEEN the layers the shapes being connected are on. This defaults to the via to cline spacing on the top layer of the design if enabled.
• Update Form Values from Saved Shape Pair Settings: This option defaults to on. When a shorting via array is created between two shapes, the tool will store the array’s parameters in the database. When these two shapes are next selected (and this option is enabled), the stored parameters will be updated to the form. This will include the values for all fields from the padstack through to the via to conductor spacing settings.
• Add Vias: Add shorting array of vias between the two selected shapes. If shorting vias between these shapes already exist, they will first be removed. This will prevent duplicate vias in the database.
• Remove Vias: If only a single (reference) shape is selected, this will remove all shorting via arrays between this shape and any other shape. If two shapes are selected, this will remove only those vias that connect specifically between the two selected shapes.

Example

Below we have a substrate with GND planes on the Surface and Base layers that we would like to connect with seed vias:

 
 
We bring up the Shape Shorting Via Array tool and set it as needed. Select the two shapes to be shorted on the work surface and then select the Add Vias button:

 
 
The shapes are now shorted together per our settings:

 

Please share your experience using this new capability!

Jerry "GenPart" Grzenia

The Allegro PCB SI Signal Setup and Audit commands were introduced in the 16.5 release. Enhancements have been made to these commands in the 16.6 release.

Read on for more details…


Selection of all Components in Component Class Setup

A new top level has been added to the tree display with a label of All Classes. Selecting the All Classes item will cause all of the visible classes and components to be selected:

More Flexibility In Creating Differential Pairs

This enhancement allows for more control over what nets or Xnets get selected to form differential pairs. You can now specify the Xnet name suffixes and differential pair name prefix as is currently allowed by the Auto Generate button on the Logic > Assign Differential Pair dialog. A new button, named Create Diff Pairs From User Defined Rules has been added to the Diff Pairs page of the SI Setup wizard:

 
When this button is selected, the following new dialog appears:

 
This dialog works the same as the Auto Generate button on the Assign Differential Pairs command. Once the two suffixes have been defined, selecting OK on this dialog causes the Setup command to look for pairs of selected Xnets that have the same base name and also have the two suffixes. A user defined differential pair will be created from these pairs of Xnets. The name of each differential pair will be the specified Diff Pair Name Prefix string followed by the base name of the Xnets. These diff pairs are then shown in the Setup Diff Pairs page of the setup wizard. You can then use the Change Selected Diff Pair to Model Defined button on this page to convert these diff pairs from user defined to model defined.

This command also handles Xnet or net names that use the bus bit format, that is, names that end with a <#>. For example, a name of DATA<3> indicates bit three in the DATA bus. When this format is used the diff pair suffixes that are specified in the above form will come before the bit number in the Xnet name. For example, there might be two Xnet names such as DATA_P<3> and DATA_N<3>. If diff pair Xnet suffixes of _P and _N are specified and the Diff Pair Name Prefix is DP_ then a diff pair named DP_DATA3 will be created from these two Xnets. This is consistent with how this case is handled by the Auto Generate button on the Assign Differential Pairs command.

User Control Over Possible Power/Ground Nets Selection

The Power and Ground Setup page of the SI Setup command shows a list of possible power and ground nets that aren’t currently marked with a VOLTAGE property. The following rules are currently used to select these nets -

•    A net that is part of a diff pair is not considered to be a voltage net.
•    A single pin net is not considered to be a voltage net.
•    If the name of the net contains any of the following strings, then the net is considered as a possible voltage net: VCC, GND, VEE, VTT.
•    If the net contains any pins that have a POWER or GROUND pin use then the net is considered to be a possible voltage net.
•    If the net contains more than a specified number of pins then it is considered to be a possible voltage net. By default this number is 25 but can be changed with the MAX_PINS_IN_NET environment variable.

The following change has been made to give you more control over how the possible power and ground nets are selected. A new button, labeled Define Possible Voltage Net Rules has been added to the Setup Power and Ground Nets page of the SI Setup wizard. This page is shown below:

 
When this new button is selected, the following dialog appears:

 
This form allows you to set up your own list of strings that will be matched against net names to find possible voltage nets. The Add and Delete buttons allow you to add new strings and delete existing ones.

The Include nets that contain power or ground pins check box allows you to turn on and off this feature. Likewise, the Include nets that contain more than XXX pins check box allows you to control this feature. The field showing the number of pins can also be updated.

The data from this form is saved with the active drawing as an invisible property on the design so they will be reused each time the drawing is opened.

Another command that looks for possible voltage nets is the Logic > DC Nets command. This command lists the nets in the design but attempts to put the nets that are most likely voltage nets at the top of the list. A new button, labeled Possible Voltage Net Rules, has been added to this form. This button opens the same form as shown above to allow you to set the rules for selecting possible voltage nets:

Improvements to Audit of Dangling Lines

This enhancement improves the audit on clines ending at a via that is a test point, as this should not be considered a dangling cline. Also dangling clines should be referred to as stubs to avoid confusion with the Dangling Lines, Via and Antenna report that is currently available.

The SI Audit command has been updated to now refer to clines that have an end point that has no connections as stubs. Also, a cline that ends at a via that has been marked as a test point will no longer be considered a stub.

Model Assignment from Assignment Map Files

The SI Model Assignment command allows you to output a record of assigned SI models into a file. There are two file formats supported - one organized by component refdes, and the other by component device type. This enhancement allows you to perform model assignments from these assignment map files.

To accomplish this, the Assign Models to Components page of the Setup wizard has been updated as shown below:

 
A new button, labeled Load Assignments From a File, has been added to this page. This button prompts you to select an assignment map file. Either type of assignment file format will be accepted, that is, a file organized by refdes or by device type. The assignments defined by the selected file are loaded. At the completion of this process a text window appear that shows the model assignments that were made and list any errors (such as model not found) that were detected. The Assign Models to Components page of the wizard will then be updated to remove all the components that now have assigned models.

Highlight Power and Ground Errors in Audit

This enhancement allows for the ability to highlight a net that has been flagged with a missing voltage property error. The RMB popup over an error shown in the Audit dialog contains a More Info About Error option for Power and Ground errors. Selecting this option provides more information about the selected error, such as why Audit thinks this net should be a power or ground net. When More Info is requested, in addition to providing the information in a confirmer, the net will be highlighted in PCB SI:

Warn User When Manually Resolving Many Audit Errors

When multiple errors have been selected in the Audit command and the Manual Resolve button is picked, you are faced with resolving each of the selected errors one at a time. The command has been enhanced to first display a confirmer that tells you how many errors have been selected and warns you that they will be resolved one at a time.

Import Errors to be Ignored in Audit

This enhancement allows for the ability to transfer the list of ignored errors from one drawing to another. To accomplish this a new button, labeled Import Report, has been added to the Audit errors page. This is shown below:

 
This button opens a file browser asking for an errors report file. This is a file that was created by the “Report” button on this same dialog. An attempt will be made to find each ignored error in the report file in the current errors list. If found and the error is currently Unresolved, its state will be changed to Ignored. This allows you to transfer the ignored errors from one drawing to another.

Edit Model Defined Differential Pairs in Setup

Currently the Setup command only allows you to update user defined differential pairs. You now have the ability to edit model defined diff pairs.

Two radio buttons have been added to the Diff Pair page of the Setup command. These buttons control whether user defined or model defined diff pairs will be listed. By default, user defined diff pairs will be displayed. By picking the Show Model Defined Diff Pairs button, model defined diff pairs will be shown. A new button, labeled Edit Model Defined Diff Pair, will be visible when a model defined diff pair is selected from the list:

 
When the Edit Model Defined Diff Pair button is selected, the pins of this diff pair are shown in the following form:

 
This is the same form that is currently available when you do a manual resolve of a diff pair connection error that is found in Audit.

Collapse/Expand Levels in the Xnet Selection Tree

This enhancement allows for the ability to expand or collapse all the items in the Xnet selection tree.

Both the Setup and the Audit commands have a page that allows you to select the Xnets. This tree can have many different levels - designs, buses, diff pairs and Xnets. If you open a number of these levels it can become difficult to find items. A right-mouse-button popup has been added that is available over any item in the tree. There are two options on the popup - Collapse All and Expand All. Selecting Collapse All will collapse the tree for the selected item as well as all of the sub-items under the selected item. Selecting Expand All will expand the selected item as well as all of its sub-items:

 

I look forward to you sharing your experiences using these new features.

Jerry "GenPart" Grzenia