The 16.6 Allegro RF SiP product has 3 major enhancements to improve your productivity.

Read on for more details …

Data Management of Virtuoso SiP Views

In release 16.6, Virtuoso SiP Architect is enhanced to support data management of SiP views through the Virtuoso Library Manager.

To enable this, files generated in the Virtuoso-SiP Layout flow are now generated in the lib:cell:view format. Starting in the 16.6 release, if you launch SiP Layout from Virtuoso and run the export chips with connectivity command, two views - connectivity and chips - are generated below the cell name. Similarly, while designing a co-design IC, when you export the die data from Virtuoso Layout Editor, the generated die abstract file, <cellName>.dia, is saved in the die_abstract view.

If you have data management enabled for Virtuoso, the following SiP views will also support check-in and check-out of the files:

•    connectivity --This view contains the connectivity.csv file with information about cell connectivity.
•    chips -- Contains package data for the symbol generated after die export.
•    die_abstract -- Contains the die data extracted as .dia file.

These views also support the Auto checkout feature. During an operation, if the view to be updated is check-in and auto checkout is enabled, you are not prompted to check-out the file.

To enable the auto checkout feature in the batch mode, you need to set the rfsip_autocheckout_batchmode environment variable. In this case, all the checkout messages are listed in the Command Interpreter Window (CIW).

Import Die Abstract Enhancements

The import die abstract feature in Virtuoso Layout Editor (VLE) is enhanced to support auto-backup of original IC-layout during die-import. You have an option to enable or disable the backup creation feature. With this option enabled, every time you import the die abstract (.dia) file, a original die layout is saved in the layout_bkup view.

Besides this, the difference viewer has also been enhanced. You can now specify the tolerance values for various properties and if the changes are within the specified tolerance, they will be ignored.

Die Abstract File Enhancements

Starting this release, when you export die data using .dia files, the shapes, such as polygons and circles, defined in the Area Transfer are also transferred. This functionality allows you to use to use die abstract files to transfer shapes -- such as company logos -- from Virtuoso SiP Architect to SiP Layout.

Please share your experience in using these new features.

Jerry “GenPart” Grzenia

The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over the next several weeks. Here are some major layout related enhancements:

• Snap Enhancements
• Add Connect Enhancements
• Modify Connectivity Enhancements
• Add Component Enhancements
• Scaled Copy Enhancements
• Single Segment Connection
• Route with Any Angle Bend

Read on for more details …


Snap Enhancements

In Allegro 16.5, when you snap an RF component to a non-RF component pad, you can only snap to the connecting point (usually it is the center of the pad). Sometimes designers want to connect RF components with non-RF components at the edge of a pad. You can use this functionality to snap an RF component to a non-RF component, or a non-RF component to an RF component or even a non-RF component to another non-RF component based on the connectivity.

There is a “Snap to pad edge” check box on the form which is used for snapping to a specific edge of a pad:

Notice: When you snap a non-RF pad edge to another non-RF pad edge, this may result in violations for manufacturing/assembly, so you’ve to manually check all those violations.

The other enhancement for snap is that you can select some components as a temp group to snap together. During the snap command, RMB select Temp Group and then click a pin to snap, the whole temp group will be moved together.

The use model for the snapping pad edge is a little different from the original snapping functionality; once the “Snap to pad edge” option is checked, the Direction for “Fix source component” or “Fix destination component” will be disabled. The source component will be attached to your mouse and you need to move your mouse close to the destination component pad edge.

Add Connect Enhancements

The Add Connect command is enhanced to support snapping to pad edge functionality. When you check the “Snap to pad edge” option (this option is available once you check the “Snap to connect point” option), you can start routing from any edge of a pad by moving your mouse close the edge of the pad and clicking it to start.

There is another option named “Variable line width”. This option will be available if the “Snap to connect point” option is checked. If you check the “Variable line width” option, the width of the RF trace will be variable based on the entry and the size of the pad and you can’t change the trace width during the routing. If you uncheck this option, the width of the trace will use the value that you entered on the Options tab and you can change the width during the routing process.

There is an extra item on the RMB menu during the routing. It’s “Accurate length”. If you select it, a form will pop up and you can enter a specific value for the length that you want to route.

You can route RF trace with any angle mitered bend by setting as following:

Modify Connectivity Enhancements

This command is enhanced by adding a “Snap to pad edge” option. If this option is checked, the following “Fix source component” and “Fix destination component” options will be disabled:

Add Component Enhancements

The Add Component is enhanced with the new option of “Snap to pad edge”. If this option is checked, the component to be placed can be located at a specific edge of a pad during the placement.

 
Scaled Copy Enhancements

This command is enhanced by increasing the option “Snap to pad edge”. Once this option is checked, the scaled copied RF component can be connected to any edge of a pad.

 

Single Segment Connection

In some cases, designers may want to connect two points (pads) with a single segment (microstrip line for example). You can use this new command by clicking RF-PCB->Single Segment Connect as below:

Route with Any Angle Bend

This is a new command to connect two pins/pads with any angle mitered bend. We’re trying to use three RF components (two line segments and one any angle mitered bend) to connect two specific pins/pads. The line segment may be Microstrip Line (MLIN) or Stripline (SLIN) and the any angle bend may be MBEND or SBEND2. Click RF-PCB->Any Angle Bend Connect to launch this command.
 

The parameters are shown on the Options tab as shown below:

 
If you have anything to share on how you’re using these new features – please do!

Jerry “GenPart” Grzenia

Placement and routing have always been an integral part of printed circuit board design. The productivity of the product is often (if not always) achieved best if the PCB has a proper placement of the components and effective routing to support the placement. With the increased complexity of the designs and smaller board sizes, routing of signals has become more challenging. Designers are always looking for ways to ease routing complexity and hence reduce the turnaround time.

Preparing the schematic & library for pin swapping

• Specify the swap properties on the pins of the component to be enabled for swapping.

 Fig 1. Package properties dialog box showing PinGroup assignment.

Specify a unique number in the PinGroup column for specific pins you want to swap within the gate/function.  Only pins with the same value of PinGroup can only be swapped. For example, if all input pins are allowed to be swapped, specify a value of 1 to all input pins and 2 to all output pins for the PinGroup property, as shown in Fig 2.

• If you are working with a split part (multi-section part) and wish to swap the pins across slots/sections, you need to have a property called SWAP_INFO specified on each of the sections as shown in the below picture:

 

Fig 2. User Properties dialog box at Library level

As per the above example, you are allowed to swap the pins across all 4 sections. If you want to restrict the pin swapping across some sections only, the value of SWAP_INFO should be changed accordingly. For e.g.: SWAP_INFO = (S1+S2),(S3+S4) will allow pin swapping between section 1 (S1) & section 2 (S2) and not with the other 2 sections (i.e. S3 and S4). Similarly, Pins between section 3 (S3) & section 4 (S4) can only be swapped within the 2 sections.

•  Generate the Allegro netlist by choosing Tools > Create Netlist > PCB Editor (tab) from OrCAD Capture

  

Fig 3. Create Netlist Dialog Box

•  Create the board automatically by checking the option "Create or Update PCB Editor Board (NETREV)" from the above UI.

Note: If you do not generate the board file during netlist creation, you could import the schematic logic to Allegro PCB Editor using the option File > Import > Logic command from within the PCB Editor.

• Once the schematic netlist is imported in Allegro PCB Editor board file, place the components on the board file and notice the unrouted connections.
• To swap the pins on the board file, select Place > Swap > Pins

 

  

Fig 4. Pin Swap command in PCB Editor   

                                                                                                                                                                                                                              

a. Select the pin on the footprint that needs to be swapped.

b. PCB Editor highlights the other available pins that can be swapped with the selected pin (from step #a). If no pins are highlighted, read the command window at the bottom for an appropriate message.

c. Select the pin from the highlighted group. Right Click > Done, to complete the swap operation.                                               

  

Fig 5. All swappable pins are highlighted in PCB Editor

Starting with the Allegro PCB Editor 16.6 release, we can compare two constraint databases and view the constraint differences. This provides an efficient opportunity for designers to determine the differences between 2 designs.

Read on for more details

Generate a Constraint Difference Report

1. Open the Constraint Manager.
2. Select File > Import >  Constraints.
3. The 'Import Constraints' dialog box is displayed. Select the 'Report Only' check-box.
4. Choose the .dcf file to compare.  This .dcf file is exported from a different database.
5. Click 'Open' to create the report.

The Constraint Difference Report is shown below:

 
In the same way you can also select File > Import >  Technology File and open a .tcf file to view the Technology Difference Report.

View a Constraint Difference Report

The report can be opened in a built-in report viewer. This viewer consists of a toolbar and view window.
Report Viewer Toolbar:

 

The table below describes the function of each tool button.
Tools                                        Function
Previous                                   Selection shows previous view of the report
Next                                        Selection shows next view of the report
Export report to HTML               Export the report as an HTML page
Print Preview                            Shows a printer-friendly view of the report
Close Window                          Closes the report viewer

Export Report as HTML

1. Select the 'Export report to HTML' button from the toolbar. The Export Report dialog box is displayed.
2. Browse the directory to save the report.
3. Provide a report folder. 'OK' button gets enabled. Select OK.

The HTML page of the report is generated. You can open the HTML report page in any browser.

Printing a Report

1. Select the 'Print Preview' button from the toolbar.  The printer view is displayed for review.

2. Choose 'Send to printer' for printing the report.

Representing Constraint Differences

The Constraint Difference Report viewer is a two-frame, tree-view based representation.

Navigation Mode

1. By Tree-view shows a summary of the selected node in the tree-view:

2. By following Links, shows a summary of an object when selecting the object name link
3. By previous and next show selections made forward and backward in the report selections

 

View Layers

There are three viewing modes:
1. Summary only (S) shows a description only with the number of changes

 
2. Differences only(D) shows Destination and Source constraints for each attribute. Unchanged layers are not shown.

 

3. All values(A) shows constraints at Destination and Source for all layers.

 

Please share your experiences using this new 16.6 capability.

Jerry “GenPart” Grzenia

Components in a design communicate with each other based on some rules or protocols. These protocols contain a group of signals with some relationships defined between them -- for example byte lanes, clock and strobes. The Allegro Design Entry HDL 16.6 release enables the use of these protocols or signal grouping by introducing support for hierarchical interface definitions.

These definitions can be entered in the design and can be saved on disk as a library for reuse purposes. This enables the system connectivity authoring at a higher level of abstraction, leading to acceleration in design intent authoring, and also communicates design intent at a higher level to the downstream processes.
 
The grouping of signals can help in planning the PCB implementation by guiding placement and converting of the groups to bundles and help in routing of the board. It can also be used for IC-Package-Board co-design.

Read on for more details …



New objects have been introduced in the tools for supporting the design flow.

Net Groups

A Net Group is a collection of net objects which is hierarchical in nature. Different types of Net Objects, such as Nets, Buses, Differential Pairs, XNets, and Net Groups, can be added as members of a Net Group. However, any net object can be a member of one Net Group only. Similarly, a Net Group can be a member of only one Net Group.

Net Groups are created on the fly using the existing design signals. They provide a higher level of abstraction and replace User Defined Buses.

Here’s an example of tapping from a Net Group:

Interfaces

Interfaces are library definition of Hierarchical Net Groups. They are defined using a special Interface Editor and can be stored on disk. They can be loaded from a formal definition on disk for instantiation in designs. The existing signals can then be mapped to the Interface instances using Auto Mapping or Manual Mapping.

Net Groups and instances of Interfaces can be used in the designs for faster design authoring.

The Old Model for representing an Interface:
–    Uses a Vector signal to model an Interface
–    Manually tap bits & enter signal name
–    Single Level of Grouping Only
–    Notes are used to map bits to signals
–    Common cause of connectivity errors
 

The New Model for representing an Interface
–    Leverage Hierarchical Net Group or Interface Object
–    No more manual mapping of signal to bit
–    Infinite hierarchical groups
–    Selection of members done using RMB menus
 

The new Design Entry HDL (DEHDL) Schematic Operations

–    Creation of Hierarchical Net Groups
      •    Schematic Selection
      •    Editor Dialog box
–    Instantiation of Hierarchical Net Groups / Interfaces
      •    Tapping out members for connectivity
–    Editing of membership of Hierarchical Net Groups
–    RMB menu provides access to all Net Group and Interface Members
–    Dynamic Net Group update by connecting named signal
–    Auto-naming using patterns
–    Navigation to instantiated objects
–    Synchronization & Cross-Probing with Constraint Manager Objects


Constraints Manager Operations

–    Creation of Hierarchical Net Groups
–    Editing of membership of non-schematic defined Hierarchical Net Groups
–    Constraining of Hierarchical Net Groups and Interfaces
•    Application of Constraints Set
•    Adding and overwrite of constraints

 



Interface-aware Placement and Routing

You can display the shape of the auto-generated Interface and the Interface hierarchy can be traversed up / down:

 

You can do route feasibility analysis, and display the entire Interface at the RatBundle display. You can easily visualize scheduling issues. RatBundles can be  edited (split, etc), but with limitations based  on Interface hierarchy:

 


I look forward to your feedback!

Jerry “GenPart” Grzenia

The Allegro FPGA System Planner (FSP) 16.6 release offers major improvements in Auto-interactive pin swap (“Planning Mode”) with the addition of “Auto pinswap” functionality. Using three different algorithms – Reassign Bundle Pins, Rake Order, and Breakout Order – you can re-optimize entire bundles (the existing 16.5 manual pin swapping functionality has been retained). The communication between Allegro PCB Editor and FSP has also been improved. Instead of using a copy of the FSP project and then side files for communicating swap requests, all communication is managed through an associated FSP project that the PCB designer selects in Allegro PCB Editor - this can be a copy of the FSP project or the master.

Read on for more details …

In the 16.5 release, the Allegro PCB Editor used placement dependent results to accomplish routing:

In the 16.6 release, the Allegro PCB Editor auto-interactive pin swap (“planning mode) uses the power of FSP during the PCB planning phase to re-optimize pin assignments based on actual bundle flows:

There are now available three (3) different auto pin swap algorithms that can be used - Reassign Bundle Pins, Rake Order, and Breakout Order:

The algorithms now combine flow/route planning along with the FPGA rules guided swapping:

I look forward to your feedback on these new capabilities.

Jerry “GenPart” Grzenia

In an interviewof Cadence Product Marketing Director Brad Griffin by EDACafe, Brad shared his enthusiasm and vision of Allegro and Sigrity integration with the audience.  “Sigrity is a world-class signal integrity and power integrity solutions provider.” he said, “so the integration of Sigrity and Allegro brings design and analysis together. If you are a board designer, you don’t need go to other tools and learn all the analysis expertise. Instead, you can just bring in some signal integrity technologies from Sigrity to finish your design work. If you are an analysis expert and you find the design is not working and you need to make changes, the Allegro technologies are there allowing you to make changes according to your needs. Allegro and Sigrity integration bridges the gap between designers and analysts.”

According to Brad, the integration of Allegro and Sigrity Signal Integrity solution is the first step of the whole integration plan. The next step will be leveraging the state-of-the-art Power Integrity (PI) technologies from Sigrity to strengthen Allegro PI solutions. This Allegro Sigrity PI solution is expected in 2013.

The 16.6 Allegro Design Workbench (ADW) Configuration Manager has been enhanced!

There is an enhanced focus on software serviceability and an improved ease of use environment for managing:

• Software updates & version status
• Configuration Files & Database updates
• Single cockpit to monitor global server topology
  • Easy to use dashboard for Server connection status
• Server topology

A new ADW Server Setup Wizard provides the ability to quickly install the server and clients.

The Sever Management Tools provide:
–    New server set up wizard
–    Start/stop server
–    Server status logs

You can now setup a schedule for Library Distribution and Distribution status monitoring.

Read on for more details …

Here’s the new Configuration Manager:

 
You can setup a Master or Design type server:


 
The new map display indicates the various servers around the globe and their status:

 

A green icon indicated the server is running (yellow means it’s stopped). You can hover over the icon to determine the name, description and status. A Right Mouse Button (RMB) on the icon controls other options:

 
Here are the various options when you select Configure Library Distribution:

 


As always, I look forward to your comments!

Jerry “GenPart” Grzenia

With the 16.6 release, you now have the capability of utilizing the PCB SI tools (SigXP) to work with topologies and constraints in the OrCAD Capture environment.

Capturing constraints early in design cycle is important for the following reasons:

• Quality challenges as the design cycle for any PCB product is shrinking day by day
• As the edge rates are shrinking, it is necessary to constrain the critical signals up-front to avoid signal integrity issues
• As a result,engineers are forced to move some of the tasks early in the design cycle, which might cause more iterations if taken at the final stage of board designing
• Enabling pre-route constraints cuts down the design iterations, enabling designers to deliver shorter design cycles

Read on for more details…

Here is an overview of the Capture – SI flow:

SI Model Management (associate models to schematic instances)
• Setting up SI Model Libraries
• Auto Generate Models for discrete components
• Assign Models to Parts and Pins

Explore Signals (associating explore signals and managing ECSets on schematic XNets)
• Export XNET to Signal Explorer (SigXP)
• Assigning topologies to schematic XNets
• Validate topologies on schematic XNets

Export/Import ECSets (exporting/importing ECSet assignments from/to the schematic)
• Export ECSets from the schematic to SI Expert
• Import ECSets to the schematic from SI Expert
• Export ECSets to physical layout
• Import ECSet changes from physical layout

Export/Import with Allegro PCB Editor (taking the ECSet to/from Allegro Layout)
• Netlisting to Allegro
• Backannotating from Allegro


There are two methodologies for managing constraints:

Please share your experiences using this new 16.6 capability.

Jerry “GenPart” Grzenia

The Allegro AMS Simulator (analog/mixed-signal) 16.6 release adds several enhancements to the Advanced Options dialog form. This enables the customizability of a PSpice simulation run, including control over convergence homotopy options, making worst-case analysis independent of RELTOL and enabling auto-convergence automatically in case of convergence failure. These options do not change the core behavior of the simulator, but provide the designer new ways to control the behavior at different simulation points.

Options have been added to the Advanced Analysis Options dialog box in the following areas:
--Bias-Point Convergence
--Integration Method
--Voltage Limiting
--Worst-case Deviations
--Max-Time Step Control
--Pseudo Transient
--Relative Tolerance

Read on for more details…


Here are the new options available in the Advanced Analog Options form:

 


Convergence Improvement Options:
– Advanced Biaspoint Convergence Homotopies
– Integration method option
– Node Value Limiting
– Relative Tolerance

Accuracy Improvement Options:
– Worst-case control independent of RELTOL
– Behavioral sources TimeStep Control for sinusoidal functions
– MinStep independent of TSTOP
– 64-Bit Data accuracy

For the Biaspoint Convergence:

• PSEUDOTRAN
  • Bias-point Convergence Enhancement
  • Used when all other methods (STEPGMIN, STEPSOURCES) have failed
• ADVCONV
  • Enables all convergence algorithms, viz. PseudoTran, StepGmin, and StepSources (ON by default)
• GMINSRC
  • Enables StepGmin from inside of StepSources
• NOSTEPDEP
  • Suppresses stepping of dependent sources during StepSources
• GMINSTEPS
  • Maximum number of steps per iteration of StepGmin
• ITL6
  • Maximum number of steps per iteration of StepSources
• PTRANSTEP
  • Maximum number of steps per iteration of PseudoTran

For the Transient Convergence:

• METHOD = [TRAPEZOIDAL|GEAR|DEFAULT]
  • Integration method to be used during Transient analysis
  • Gear is more stable, so more often used in the default mode
  • Trapezoidal is more accurate
• TRTOL
  • Tolerance for integration error calculated during transient analysis
  • A higher value implies more tolerance, so bigger time steps and reduced accuracy
  • Can be useful to jump model discontinuities in case of fastswitching designs
  • Default = 7

There are also new PSpice Options:

• LIMIT
  • Absolute limit on data values calculated in PSpice engine during simulation
  • Can be used in case of overflow errors
  • Can also be useful for convergence failures in some simulations
• WCDEVIATION
  • Deviation to be used for Worst-case analysis
    • Default calculation for worst-case Delta is nominalValue * RELTOL
    • If WCDEVIATION is specified, it gets modified to nominalValue * WCDEVIATION
• PROBE64
  • 64-bit Probe data
  • Increases resolution of probe
  • Very useful for differential probes
• NOGMINI
  • Suppress GMIN addition across current sources
  • Gives more accurate results for very low current values
• BRKDEPSRC
  • Sets automatic break-points for sinusoidal behavioral sources
  • Useful for long simulations when default Max Time Step is too big

I look forward to your feedback!

Jerry “GenPart” Grzenia

The Allegro PCB Editor Place Replicate application now supports the processing of component reference designators. The work performed in customizing assembly text or silkscreen to the seed circuit can now be leveraged across the replicated modules.

Read on for more details…

In the image below there are two modules. The one on the left (U14, U15 and the associated capacitors) has the text moved to locations which were determined to be appropriate. The module on the right would need to be updated to reflect the same text placement:

 
Once you have customized the text locations, use the Place Replicate 'Refresh' application to update the second circuit. The steps are:
1.    Set the 'Super Filter' to 'Module'
2.    Hover over the seed circuit then RMB — Place replicate — Update. Select/unselect additional etch as needed.
3.    RMB — Done. This will launch the file browser UI in which you can select the module you would like to refresh. Selecting the module and performing a save will update the module on disk and update the module(s) in the design.
 
 

As always, I look forward to your comments about this new capability.

Jerry “GenPart” Grzenia

Cadence IC Packaging tools today provide a spreadsheet-based import mechanism for die and BGA (standard) components, as well as for importing of netlist updates. In certain design scenarios, particularly for leadframe package designs, it is also desirable to be able to import a similarly formatted file to define the bond wire connections in the design. In this way, when an updated component is brought into the design from another tool, the bond wire text file can be used to quickly update the mapping of pins to leads/fingers/etc. It can also be used to read updated information from the package manufacturer if changes need to be made to the wire profile assignments.

The 16.6 Allegro Package Designer (APD) product provides this capability.

Read on for more details …
 
This tool does not import existing customer flows. It provides a new mechanism for importing bond wires into the design, and may be used in place of the “wirebond add,” “wirebond import,” or SKILL commands to create bond wires in the design. 
  
  
Menu
 
Menu Pick: Route  > Wire Bond > Bond Wire Text Import:

 
 
Command-Line Access

Command line: bondwire text in
 
Example

We have a die we need to import bond wires into:

 
 
Upon launching the tool, you must select the text file to be imported:

 

The text file provided must have information for each bond wire being imported:
 
     1.  Start location of each wire: X/Y coordinate and the layer name
     2.  End location of each wire: X/Y coordinate and the layer name
 
Wire profile – Optional. If not set the tool uses the default profile for design.
 
This text file contains the information mentioned above:

 
 
 
 
Once selected, you can select the delimiter and units before proceeding to the main wizard page to select the columns of information (if not automatically detected from the header line in the file):

 
 
From this file, if any padstacks are not defined, the wizard page to define them will be presented.
 
In this next step we must set the columns to accurately represent their contents.  
The graphic below shows the information needed to import wire bonds.
Using the RMB we can set the columns as needed:

 
 
On the final page of the wizard, you can confirm the results and commit to the database.
The wires are imported as shown below:

 
 

I look forward to your comments on using this new 16.6 capability!

Jerry "GenPart" Grzenia

Feedback regulation loops are widely used by power electronic designers. It is one of the most important and sensitive parts of a power supply circuit. An incorrect feedback loop design may cause oscillations in the circuit, and also increase the output voltage drops. In order to achieve a stable and tight regulation in the output, it is important to have a correct feedback loop.

To test a feedback loop, generally engineers use trial and error methods with the hardware. This takes a lot of time and labor. Moreover, it is expensive because components and/or PCB boards can be damaged. AMS Simulator (also known as PSpice) can be used by designers to test their loop designs without using any physical hardware circuits, and in the process save a lot of time and cost that goes into fine-tuning the design.

You can get a copy of a sample regulation loop circuit created in PSpice along with the simulation results: 

To download the Database Click Here
To view the Datasheet Click Here

To demonstrate a regulation loop and compensator circuit, an example circuit is designed with the MAX8566 component and is available in the Cadence PSpice library.

There are two sections: Open loop design and closed loop design.

Open loop design

You can create an open loop design using the Cadence AMS Simulator (PSpice) tool. Using the component MAX8566available in the Cadence PSpice library, and the datasheet for MAX8566, you can implement an open loop design as per the following figure:

In the open loop design there is no feedback. So the output will increase or decrease with the variation of input voltage. The output voltage is not controlled -- hence V(out) increases as the input voltage increases. The goal is to get a constant 1.9 Volts at the output with a variation of input from 2.3 Volts to 3.6 Volts.

The figure below shows the output voltage waveform when the input supply is at 2.3 Volts, and V(out) = 1.9 Volts

The figure below shows the output voltage waveform when the input supply is at 3.6 Volts, and V(out) = 2.94 Volts

So, the output voltage V(out) increases from 1.9V to 2.94V when the supply voltage increases from 2.3V to 3.6V.

Closed loop design
 

From the datasheet of MAX8566, Pin 2 is the error amplifier output and Pin 32 is the feedback input.
Pin 25, REFIN, has the reference voltage, which is compared with feedback voltage (FB) to control the pulse width.

From the output filter the corner frequency of the circuit can be calculated as follows:  

fcorner=1/(2*Π*√L1*C1)  
Since C1 = 33μF, L1 = 200μH, fcorner ~= 2.0 KHz  

The filter gives two poles at 2.0 KHz. These two poles produce a phase shift of 180° that makes the output oscillatory. Hence two zeros have to be introduced to cancel the complex poles at the corner frequency and another pole at the origin. This gives a single slope (-20dB/decade) crossing at the ‘0'dB axis, which makes the loop stable. The pole at origin also decides the bandwidth of the converter.

Following the above discussion compensator circuit should have Pole at ω = 0 Hz and Zero at ω = 2 KHz, 2 KHz

Considering all practical conditions, it is advised to choose the Zero location at 1/10th of the calculated value.

For this design, Zeros can be considered at 200Hz. If the transfer function of the following circuit is derived, you can see that there are two zeros at fz1 and fz2 with one pole at fp where

fz1 = 1/(2*Π*R37*C10)= 200Hz
fz2 = 1/(2*Π*R32*C3)=200Hz
fp = 0Hz

After doing all the above changes, the design is ready for closed loop simulation. If simulation is run, following results appear in the PSpice probe window.

The voltage at OUT is constant V(out) = 1.9 Volt.The user can vary the input supply from 2.3 Volt to 3.6 Volt. The output voltage will be constant at 1.9 Volt. There is no oscillation at output voltage and it is stable.

Refer to the complete AppNote for a detailed procedure about each of the steps involved in the process.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Placement and routing have always been an integral part of printed circuit board design. The productivity of the product is often (if not always) achieved best if the PCB has a proper placement of the components and effective routing to support the placement. With the increased complexity of the designs and smaller board sizes, routing of signals has become more challenging. Designers are always looking for ways to ease routing complexity and hence reduce the turnaround time.

Preparing the schematic & library for pin swapping

• Specify the swap properties on the pins of the component to be enabled for swapping.

 Fig 1. Package properties dialog box showing PinGroup assignment.

Specify a unique number in the PinGroup column for specific pins you want to swap within the gate/function.  Only pins with the same value of PinGroup can only be swapped. For example, if all input pins are allowed to be swapped, specify a value of 1 to all input pins and 2 to all output pins for the PinGroup property, as shown in Fig 2.

• If you are working with a split part (multi-section part) and wish to swap the pins across slots/sections, you need to have a property called SWAP_INFO specified on each of the sections as shown in the below picture:

 

Fig 2. User Properties dialog box at Library level

As per the above example, you are allowed to swap the pins across all 4 sections. If you want to restrict the pin swapping across some sections only, the value of SWAP_INFO should be changed accordingly. For e.g.: SWAP_INFO = (S1+S2),(S3+S4) will allow pin swapping between section 1 (S1) & section 2 (S2) and not with the other 2 sections (i.e. S3 and S4). Similarly, Pins between section 3 (S3) & section 4 (S4) can only be swapped within the 2 sections.

•  Generate the Allegro netlist by choosing Tools > Create Netlist > PCB Editor (tab) from OrCAD Capture

  

Fig 3. Create Netlist Dialog Box

•  Create the board automatically by checking the option "Create or Update PCB Editor Board (NETREV)" from the above UI.

Note: If you do not generate the board file during netlist creation, you could import the schematic logic to Allegro PCB Editor using the option File > Import > Logic command from within the PCB Editor.

• Once the schematic netlist is imported in Allegro PCB Editor board file, place the components on the board file and notice the unrouted connections.
• To swap the pins on the board file, select Place > Swap > Pins

 

  

Fig 4. Pin Swap command in PCB Editor   

                                                                                                                                                                                                                              

a. Select the pin on the footprint that needs to be swapped.

b. PCB Editor highlights the other available pins that can be swapped with the selected pin (from step #a). If no pins are highlighted, read the command window at the bottom for an appropriate message.

c. Select the pin from the highlighted group. Right Click > Done, to complete the swap operation.                                               

  

Fig 5. All swappable pins are highlighted in PCB Editor

Feedback regulation loops are widely used by power electronic designers. It is one of the most important and sensitive parts of a power supply circuit. An incorrect feedback loop design may cause oscillations in the circuit, and also increase the output voltage droops. In order to achieve a stable and tight regulation in the output, it is important to have a correct feedback loop.

To test a feedback loop, generally engineers use trial and error methods with the hardware. This takes a lot of time and labor. Moreover, it is expensive because components and/or PCB boards can be damaged. AMS Simulator (also known as PSpice) can be used by designers to test their loop designs without using any physical hardware circuits, and in the process save a lot of time and cost that goes into fine-tuning the design.

You can get a copy of a sample regulation loop circuit created in PSpice along with the simulation results: 

To download the Database (Created with Allegro Design Entry Capture) Click Here
To view the Datasheet Click Here

To demonstrate a regulation loop and compensator circuit, an example circuit is designed with the MAX8566 component and is available in the Cadence PSpice library.

There are two sections: Open loop design and closed loop design.

Open loop design

You can create an open loop design using the Cadence AMS Simulator (PSpice) tool. Using the component MAX8566available in the Cadence PSpice library, and the datasheet for MAX8566, you can implement an open loop design as per the following figure:

In the open loop design there is no feedback. So the output will increase or decrease with the variation of input voltage. The output voltage is not controlled -- hence V(out) increases as the input voltage increases. The goal is to get a constant 1.9 Volts at the output with a variation of input from 2.3 Volts to 3.6 Volts.

The figure below shows the output voltage waveform when the input supply is at 2.3 Volts, and V(out) = 1.9 Volts

The figure below shows the output voltage waveform when the input supply is at 3.6 Volts, and V(out) = 2.94 Volts

So, the output voltage V(out) increases from 1.9V to 2.94V when the supply voltage increases from 2.3V to 3.6V.

Closed loop design
 

From the datasheet of MAX8566, Pin 2 is the error amplifier output and Pin 32 is the feedback input.
Pin 25, REFIN, has the reference voltage, which is compared with feedback voltage (FB) to control the pulse width.

From the output filter the corner frequency of the circuit can be calculated as follows:  

fcorner=1/(2*Π*√L1*C1)  
Since C1 = 33μF, L1 = 200μH, fcorner ~= 2.0 KHz  

The filter gives two poles at 2.0 KHz. These two poles produce a phase shift of 180° that makes the output oscillatory. Hence two zeros have to be introduced to cancel the complex poles at the corner frequency and another pole at the origin. This gives a single slope (-20dB/decade) crossing at the ‘0'dB axis, which makes the loop stable. The pole at origin also decides the bandwidth of the converter.

Following the above discussion compensator circuit should have Pole at ω = 0 Hz and Zero at ω = 2 KHz, 2 KHz

Considering all practical conditions, it is advised to choose the Zero location at 1/10th of the calculated value.

For this design, Zeros can be considered at 200Hz. If the transfer function of the following circuit is derived, you can see that there are two zeros at fz1 and fz2 with one pole at fp where

fz1 = 1/(2*Π*R37*C10)= 200Hz
fz2 = 1/(2*Π*R32*C3)=200Hz
fp = 0Hz

After doing all the above changes, the design is ready for closed loop simulation. If simulation is run, following results appear in the PSpice probe window.

The voltage at OUT is constant V(out) = 1.9 Volt.The user can vary the input supply from 2.3 Volt to 3.6 Volt. The output voltage will be constant at 1.9 Volt. There is no oscillation at output voltage and it is stable.

Refer to the complete AppNote for a detailed procedure about each of the steps involved in the process.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models.

Read on for more details …


Adding Vias

Adding a via is easier and faster than before. You no longer have to go through the Via Model Generator to create a model nor are you required to search the list of existing models that fit the need. The difference is that you are now adding a via rather than a via model. The via may not be pre-solved to a specific model.

The current way of adding a via in SigXp is still supported and unchanged. You can still add a via model on the canvas.

In order to add these “dynamic” vias in SigXp, a layerstack will have to be present in the topology. In a new topology this can be accomplished by using the Manage LayerStacks function to create or import a layerstack. When a topology is extracted from Allegro, the layerstack of that board is automatically imported in the topology.

A new via is added with two nodes (two connection points) on the canvas. When newly added, the two nodes are not tied to any specific layer as they will take on the properties of the connected node, so the label of those nodes will be Layer1 and Layer2:

 
If a trace is connected and is on a particular layer then the via node is assumed to be on that layer and will take its properties. In the case of a "floating trace" (a trace not on a layer stack layer), the via node will take its properties and still say LayerX (unchanged). Since we do not know what layer that is, we will assume the top or bottom most layer of the via structure:


 
The prior release (16.5) via toolbar button is a two-part button which lists all available via models on the right hand side pulldown:


 
Clicking on the left side of the button (the one with the via image) brings up the Add Element Browser. In 16.6, the left part of the Add Via button will add the new “dynamic” via with only two nodes. The pulldown remains unchanged to list the pre-solved via models.

Reuse of Via Models

You will want to reuse already solved via models in SigXp. To do that, the same technique used today is available. You can either select the right button of the Add Via toolbar button, which will list all existing via models available sorted by types, or RMB > Add Element can still be used to choose the desired via model.

When these via models are added to the canvas, the model is “locked” to the via and cannot be changed - this is the via model that will be used to simulate.

Via Parameters

The new (dynamic) via has the following parameters which are listed in the standard parameters spreadsheet. These parameters can be modified:

 
model    The via model associated with the via. A via which has no model yet will have UNMODELED as a model. Once solved, the name of the model will be used.
viaOutputFormat    The format with which the model was solved. If no model exists yet, the format is blank.
viaPadstack    The name of an available padstack. This parameter is a pulldown which lists the available padstack files on disk and in the library.
viaTopLayer    The top most layer of the via drill.
viaBottomLayer    The bottom most layer of the via drill.

For coupled vias the parameters will be a little different. It will show the via name with which it is coupled as well as the distance between them. Aside from that, it will look just like a single via.

Padstack Consumption

SigXp can now consume and optionally modify the same padstacks as Allegro PCB Editor. You can to import *.pad files and keep them as file if they are different than the library.

You can access the Via Padstack Manager through the menus using Setup > Manage Via Padstacks, or by right clicking in the SigXp canvas and selecting Manage Via Padstacks. Editing or creating a new padstack will use the same padstack editor available in Allegro. The padstack can be saved as an external file. If shapes are associated with the padstack, they will be stored in the same location. All information in the padstack relevant to the via is used to generate the model:


 

Via Modeling

When a new “dynamic” via is added to the topology, no model is associated with it. Only when you perform a simulation or manually solve the via will the field solver be called. In batch mode, the field solver uses the standard via modeling preferences that are currently found in PCB SI. These settings are available in SigXp and can be accessed through the menus using Analyze > Via Setup Preferences or by right clicking in the SigXp canvas and selecting Via Setup Preferences:


 
The via subckt section is built using the padstack information, the layerstack and the connected traces, as is done in Allegro PCB SI. The via model is stored in the working IML file.

Coupling Vias

With this feature, you can couple 2 single vias to form one single model. You can select 2 vias in the SigXp canvas and select Couple from the right mouse button menu:


 
When the Couple function is used, you will be required to specify a spacing between the vias:


 
This spacing is added to the parameters in the spreadsheet:


 
When you select a coupled via, all vias in the set will be selected:


 
You can decouple the vias by selecting Decouple from the right mouse button when one of the vias is selected:



Please share your experiences using these 16.6 features.

Jerry "GenPart" Grzenia

The 16.6 Allegro RF PCB application has many new enhancements.

I’ll cover a few over the next several weeks. Here are some major autoplace related enhancements:

• Grouping in Design Entry HDL (DEHDL)
• Allegro PCB Editor Enhancements

Read on for more details …

Autoplace is a very important step for RF layout after the schematic is transferred to PCB layout. The system will automatically create groups based on connectivity during the autoplace process. This will result in many groups in autoplace and it’s difficult to find the proper groups to do autoplace. Designers like to define groups in the schematic based on functions such as LNA, pre-amplifier and so on and then select the proper groups to start autoplace.  

In 16.6, we’ve added some new commands in DEHDL to support grouping, such as add group, disband group, display group and so on. In this case, designers can easily control the groups for autoplace. The detailed commands are:


 

• Add Group will attach a property (RFGROUP) to the selected components.
• Add Split will attach a property (RFSPLIT) to the wires selected. If a wire is attached with this property, then the logic group will be broken at here (one big logic group will be split into two logic groups).
• Disband will remove the RFGROUP property from each RF component for the specific group.
• Exclude will remove the property for selected objects (RFGROUP for RF components or RFSPLIT for wires).
• Display Group will highlight/report the RF components within a specific group.
• Display Split will highlight all wires with the RFSPLIT property.

All these commands are only available in the DEHDL pre-selection mode.

When you transfer the schematic to layout and launch autoplace, you will see the groups are classified differently, the group names added in schematic are reflected in the autoplace form:


 
You can use the Group filter to easily find/locate some specific groups to do autoplace.

RF Grouping in the Front End (DEHDL)

To use the grouping functionality in the schematic, you need to select Tools->Options and check the “Enable Pre-select Mode.” You will see the RF PCB menu as follows:

 


If you check “Enable Windows Mode” as well, then Import IFF… item will not be available under the RF-PCB menu. You can find it from File->Import->Import IFF…->RF-PCB.

Add Group

You need to first select some RF components (or non-RF components) and then click RF-PCB->RF Group->Add Group. The following dialog will pop up:


 
You can enter a new group name or select an existing group from the drop-down list. If the existing group includes elements outside the current page, you need to select Module radio option. You can only select the components in current page to add to a group.  

Add Split

Select a wire or multiple wires and then click RF-PCB->RF Group->Add Split. The RFSPLIT property will be attached to the wires selected. You can’t select wires crossing pages to add split. That means you can only select the wires in the current page for this command.

For example, in the schematic, two wires are attached with the RFSPLIT property as following:

 
There will be three logic groups in the layout for autoplace even though they are actually connected together logically:




Disband

Click RF-PCB->RF Group->Disband. The following dialog will appear:


 
All available groups will be listed in the drop-down list. Select a group and select the proper scope and then Apply to disband the group. The RFGROUP property will be removed from each component of the group.

Exclude

Select one or more components with the RFGROUP property attached or one or more wires with the RFSPLIT attached and then click RF-PCB->RF Group->Exclude. The property will be removed for the selected objects. This command also works for the current page objects only.

Display Group

Click RF-PCB->RF Group->Display Group. The following dialog will appear:


 
You can display one group from the drop-down list or all groups by selecting All from the drop-down list. To display a group including elements in other pages, you can select Module radio option. Click Apply or OK. All components within the selected groups will be listed in the command line if the module option is selected, and the components of the selected groups will be highlighted in the current page.

Display Split

Click RF-PCB->RF Group->Display Split. The following dialog will appear:


 
OK to highlight the wires with the RFSPLIT property in the current page. To get the description of each wire with the RFSPLIT property within the current page, select Page option. To get the description of each wire with the RFSPLIT property in the whole design, select Module option.

Enhancements in Back End (Allegro PCB Editor)

In layout, launch RF-PCB->Autoplace. The dialog will appear:



All components will be classified into different logic groups. Each logic group will have a name with the prefix “_rfGroup”. If you have already defined a group in schematic (for example ABC), then this name will be the name for a real physical group in layout. This name will be attached following the logic name within brackets such as _rfGroup1(ABC).

Some other enhancements for autoplace are:
•    Add a new check box “Ignore FIXED property”
•    A new mark “A” for the groups just completed autoplace
•    A filter to find/locate a group
•    Ratsnests display during autoplace
•    Moving clearances
•    Performance enhancements
 
If you check the “Ignore FIXED property” option, then a fixed component can be moved as well during the autoplace.
There are two kinds of marks for the groups. A group with a “P” mark means this group is already placed into canvas before the autoplace command launched. A group with an “A” mark (green color) means this group completed the autoplace in the current session. A group without any marks means this group is still unplaced and you may need to do autoplace for it.
The autoplace is enhanced to show the ratsnests while the dynamic path is attached to your mouse during the autoplace process. This makes it is easy for you to place the group to the proper location:


 
Another enhancement is to support the clearance moving as well for the autoplace--for example, after completing the autoplace for a logical group and then adding the clearances for the components within the group. If you redo the autoplace and move to a different location to place the group, the clearances will be moved as well. Before that, the clearances will not go with the RF components:

 

Please share your experiences using these new capabilities.

Jerry “GenPart” Grzenia

Beginning with the Allegro PCB Editor 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer types. Currently, a GCSF supports four types of layers: TOP, INTERNAL (internal signal), PLANE, and BOTTOM.

Importing a GCSF will not update the design’s cross-section, but will update the design’s constraint information (electrical, physical, and spacing) based upon the current import modes (overwrite, merge, and replace).

When a GCSF is imported into a board, constraints from that techfile will be mapped as follows -
1.    TOP - TOP (topmost etch layer)
2.    INTERNAL - signal layers between TOP and BOTTOM
3.    PLANE - all plane layers
4.    BOTTOM - BOTTOM (bottommost etch layer)

Generating a GCSF

1. Open an existing board or create a new one and edit constraints.
2. In Constraint Manager, use File > Export > (Technology file or Constraints file):

 
3. Select  the “Generic” radio button  in the “Export cross-section” section.

The “Generic” radio button is enabled only if the “Physical & spacing constraints” box is checked.
The “Configure” button is enabled only when the “Generic” radio button is selected.
The “None” radio button is enabled only if “Physical & spacing constraints” box is not checked – otherwise cross-section data is necessary.

4. Click the “Configure” button if you want to select the layers you would like to use as TOP, BOTTOM, INTERNAL, and PLANE (layer mapping):


 
This step is optional. If generic cross-section is not configured, the default mapping will be used.
User selections are remembered only for the current dialog form – when you invoke the export dialog again, the default mapping will be used.

Default mapping:

    TOP:            first etch layer

    INTERNAL:   first signal layer after TOP

    PLANE:        first plane layer

    BOTTOM:     last etch layer


To exclude a generic layer from the techfile, select <IGNORE>:



In the situation shown in the screenshot above, the resulting generic techfile will have only three generic layers – TOP, PLANE, and BOTTOM.

Importing GCSF

Open Constraint Manager and select File > Import > (Technology file or Constraints file).
Select the GCSF that you have exported from a different database and choose an Import Mode (overwrite, merge, or replace).

If in the imported GCSF some of the generic layers are ignored, then layers matching the ignored layer will not be changed. This is what the report will look like:

 

Note: When a GCSF is imported, the cross-section of the original board stays intact (i.e. the number of layers, their names, and characteristics remain as before importing; only the Csets are imported).

The GCSF techfile units will behave the same way as any other techfile units. A suggested approach would be to have the same units used in both the original and the target board.


I look forward to your feedback!

Jerry “GenPart” Grzenia

The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare two databases for constraint differences. The databases that can be compared are of the following types:
• Schematics (.cpm)
• Layout design (.brd, .sip, .mcm)
• Constraints Manager Database (.dcf, .tcf)

The Constraint Comparison Utility can be used for comparing two different revisions/versions of the schematic or board databases. This utility can also be used for comparing the schematic database with the board database. A report is generated as a result of the comparison and lets you see all the changes which have been made to the design database since it was last synced up. This report helps you ensure that none of the constraints are conflicting and thus might overwrite on sync up.

The utility can be integrated in any of your design flows where you feel that you need to see the constraints differences in two databases before proceeding further in the design.
The utility can be invoked from the command line using command cmDiffUtility. This command launches the Cadence Constraints Differencing Utility dialog box, as shown below, where you can specify the two databases which need to be compared for constraints differences:

The   button (browse) can be used to select the database. Once you click this button, the file selection dialog box appears. This dialog box displays the files based on the file type filter. By default the filter is set to “Constraints Files (*.dcf, *.tcf)”.

You can select any of the following options to change the filter setting and select appropriate databases:

 

Once both the databases are selected, the “Compare Files” button is enabled. Click this button to start the database comparison. The results of comparison between the two databases are reported in a Firefox window:

 

The report is displayed as a single screen, with two frames – left frame containing the object tree and the right frame containing the details of the selected tree item.

The complete report contains hyperlinks and helps in navigating through any of the objects within the various tools – Design Entry HDL, Allegro PCB Editor, Constraint Manger. When you click a category in the tree in the left frame, the details containing lists of all the objects of that category are opened in the right frame. These details contain the object name and brief description of the changes observed.

All the object names are also hyperlinked. You can click any of the objects to view more details. The object names are also visible in the tree view in the left frame, and the detailed view can also be opened by selecting the object name there. Since the different object categories are listed in the tree view, you will notice that you can navigate to the same difference from multiple places. 

Jerry “GenPart” Grzenia

The 16.6 Allegro FPGA System Planner (FSP) product has an extremely helpful Design Compare capability.

With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP Design Compare form compares two FSP designs and is similar, but not identical, to the one used in Allegro PCB Editor.

The Design Compare form

Design Compare is a stand-alone form – it does not require the master, or any other design, to be open in FSP.
Click on the Design Compare icon or use the File > Design Compare pull-down:
     

 
In the Design Compare form, select the PCB copy on the right and the master design on the left (the order does not make a difference, but it’s easier to track differences if the master design is on the left).

Click the Compare button.

The “Show Only Diff” button helps to focus in on the differences. This is a “sticky” button – click to turn it on, click to turn it off.

The green arrows between the two sides and the yellow arrows at the top perform identical functions.

“Merge All To Left” and “Merge All To Right” will sync the designs in one step:

The FSP version of Design Compare is a little different than the one used in Allegro PCB editor. For one, there is no cross-probing in FSP like there is in Allegro. Also, in Allegro, the sections (connectivity, placement/ref des, etc.) are shown as tabs because the differences are displayed as a flattened list, for the entire design. In FSP, the items are displayed hierarchically and are selected from a drop-down:

 

Placement differences between the PCB copy and the FSP master are shown textually and graphically:

 



Merge the changes

You can merge all of the PCB changes into the FSP master. Click the “Merge All To Left” button:

 



You may encounter situations where an attempt to merge one signal(s) forces the merge of other signals:

 

This could happen if there is a cyclic dependency in the net connectivity. For example, if net n1 has to be moved to pin B26 and B26 is currently connected to net n2, then n1 and n2 are dependent nets. In other words, they both have to be moved together.

Please share your experiences using the FSP Design Compare capability.

Jerry “GenPart” Grzenia