There are several new enhancements associated with the 16.6 PCB SI Channel Analysis (CA).

Read on for more details …

SigXplorer has been enhanced to provide greater flexibility associated with AMI model management. Experimentation with buffer and AMI combinations, until this release, required joining them at the library level. No manipulation could be done in SigXplorer. Now, the 16.6 release provides canvas-level editing options, allowing you the ability to join any packaged IBIS buffer to any existing AMI model. Additionally, the influence from the AMI portion of the buffer models can be suspended (ignored) without deleting the AMI model entirely. For convenience, the AMI enable/disable as well as the AMI add/remove are all directly accessible from the SigXplorer canvas.

Adding AMI models

To add an AMI model to an existing buffer, right click on the buffer and select Add AMI Model:

 Similarly, you can remove an AMI model by right clicking on the buffer and selecting Remove AMI Model:


          
Enabling and disabling AMI models

SIgXplorer provides you with a command to disable and enable an AMI model on an IBIS device, Tx or Rx. After disabling the AMI model on a device, you can run simulations without taking the AMI model into account. The Disable AMI command, which appears on the pop-up menu when you right-click a device, can be used when you want to establish a baseline simulation result with the analog buffers and the channel but without the AMI model.
When you disable an AMI model, a slanted line appears across the AMI model icon graphic indicating that it is disabled:

 You can re-enable the AMI model on a device using the Enable AMI command, which appears on a device on which AMI was previously disabled:

          
GUI overhaul

The user interface has been completely updated in the 16.6 release. On-screen guidance is included both in the form of the task description block and as a 1-line “reminder” when the mouse hovers over a command.

All of the commands have been organized by function, with each function represented as a tab on the form. Settings can be saved and retrieved for all tabs simultaneously using a configuration file. Each option has been assigned a meaningful default value to enable quick simulations from the Action buttons along the base of the new GUI. Incremental improvements have been added in every functional tab. Characterization has been enhanced to allow import from third-party simulators. The outputs from Channel Analysis are now configurable and include new options for Time Domain and Voltage BER (bathtub) curves. Quick launch buttons combined with “.cacfg” file, and “.top” files yield three-click net checks.

Characterization tab
This tab contains options to set up the characterization. You are now able to import a characterization using the Import Characterization option. The characterization is represented as an impulse response. The input file is an ASCII file with two columns of data. The first column contains a time and the second column contains a voltage:

 Stimulus tab

Preferences tab 
 
 

 Output tab

You are now able to see a snapshot of the time domain waveform after it has been processed by the AMI models. The input stimulus waveform along with the clock ticks will also be saved for the time duration specified. You will be warned if you select more than 5000 bits at a time as selecting a longer bit duration will adversely impact both the simulation time and the size of the files. The start bit must be a number between 0 and the total number of bits. The end bit must be a number between the start bit and the total number of bits. The output waveforms will be saved in text files and saved in the results directory.

Vertical bathtub curves that show the voltage (vertical axis) opening of the eye have been added to the horizontal bathtub curves (representing the eye width in the UI). The bathtub curves predict BER up to the desired limit (default 1/10e15):

 
 Advanced features tab

 

Crosstalk implementation

One of the most important requirements of high-speed simulation is to be able to perform accurate and reliable crosstalk simulation for a topology/layout with multiple driver/receiver pairs that are electrically coupled to each other. The presence of AMI models on each of the drivers and receivers mean that the effect of equalization (or any other algorithmic effect) must be accurately captured in the simulations on a particular victim receiver from adjacent aggressors.

Channel simulation with multiple electrically coupled Tx/Rx pairs is possible with reasonable accuracy. Each channel (both aggressors and victim) is characterized individually. Simulations are performed to obtain the waveform results for the victim Rx. To perform the simulation for the victim Rx, the impulse matrix for the channel constitutes the impulse response of the primary victim as well as the crosstalk impulse responses from the aggressors. The crosstalk impulse responses of the aggressors are subjected to the Init functions of the aggressors and they can be modified by the Init functions of the aggressors. The crosstalk for AMI models/simulation is illustrated in the following example with three Tx/Rx pairs:

 
In this example, the middle channel (Tx2/Rx2) is the victim channel, while the other two channels (1 and 3) are aggressor channels. IR1_1, IR2_2, and IR3_3 represent the primary channel impulse responses for the three channels, while IR1_2 and IR3_2 represent the impulse responses of the crosstalk channel from Tx1 to Rx2 and Tx3 to Rx2, respectively. The impulse matrix presented to the init function of Tx1 will have IR1_1 and IR1_2 in the first and second columns respectively. Similarly, the impulse matrix for the init function of Tx3 will have IR3_3 and IR3_2. Depending on the AMI model, the init functions of the Txs may or may not modify the IRs presented to them. Assuming that they do, the crosstalk IRs will change to IR1_2' and IR3_2'. These two IRs are used to construct the final IR for the victim Rx which will have IR2_2', IR1_2', and IR3_2' in the first, second, and third column of the impulse matrix. Any AMI simulation with this IR will incorporate the crosstalk effects of the AMI models as well as the traditional crosstalk.

I look forward to your feedback from using these new capabilities.

Jerry “GenPart” Grzenia

In most FPGA-based boards, the PCB designer is on his own -- with little help from any tool -- to unravel what is often a routing nightmare. This can be caused by FPGA and/or schematic designs that have given little thought to the actual routing, inclucing layer stackup, crossovers, differential pair length matching, and high-speed signal integrity requirements. 

To be fair, this is not completely the fault of the upstream designers, since they also have no tools to provide PCB guidance when they make their pin assignment choices. So, they do what they can and then work with the PCB designer later -- in a painful, endless series of negotiations -- to untangle the signal spaghetti, as this DDR3 example (using actual FPGA-tool-defined pin assignments) illustrates:

Figure 1 - Typical DDR3 pin assignments received by a PCB designer

The result is that system design processes continue to suffer from a lack of the right knowledge at the right point in the process.

For example, consider a simple, two component design -- two FPGAs connected through a 32-bit data bus.  Suppose that the FPGA designer has used the FPGA design tool to pick pin assignments with the assumption that the two FPGAs will be placed side by side.  Lacking intrinsic information about the PCB, the FPGA designer can't, at least natively within his tools, use component proximity to help guide him in his pin assignment effort.  Also, since he can edit only one FPGA at a time, he has to have separate projects for each FPGA (although the tools would at least give him the ability to spread the 32 data bits across the appropriate side of each FPGA).

While a straightforward, side-by-side topology like this example is easy for an FPGA designer to envision, an FPGA is usually interconnected to several components and in some cases there are multiple FPGAs interfaced to multiple components and other FPGAs.  Then, PCB placement becomes almost impossible to visualize because the FPGA tools simply do not account for the spatial qualities of the board.

Another way to create the initial FPGA pin assignments is to use a board-aware FPGA I/O planning and pin assignment tool like Cadence's Allegro/OrCAD FPGA System Planner.  Since Allegro/OrCAD FPGA System Planner understands component placement, it uses this information, along with FPGA pin assignment rules, to automatically assign FPGA pins to signals that are optimized for both domains -- FPGA and PCB.

Allegro/OrCAD FPGA System Planner (FSP) can be used in multiple ways.  The user can derive the pin assignments in Allegro / OrCAD FSP and pass those to the FPGA designer for FPGA simulation/verification, or the FPGA designer can pass the FPGA tool's pin locations into Allegro/OrCAD FPGA System Planner, which can then by optimized for routing on the PCB.  This allows the Allegro/OrCAD FPGA System Planner user and FPGA designer to converge on an agreeable first-pass set of assignments up front, at the beginning of the process.

Figure 2 - Allegro/OrCAD FPGA System Planner

Regardless of how the pin assignments are created, either with the FPGA tools or with a tool like Allegro/OrCAD FPGA System Planner, or both, numerous FPGA and design constraints have to be managed:

• What are the electrical characteristics for the pins on the FPGA and connected parts?

            o What about the FPGA power and voltage reference pins and how do those change as the pin assignments change?

            o Most I/O pins are multi-use pins but many are not -- which ones are which?

            o How do the configuration and JTAG pins need to be connected?

• What are the signal requirements?

            o Are there high-speed buses, whose signals should be kept together, like a byte lane of a DDR interface?

            o Do some signals have to connect to dedicated FPGA pins, like clock-capable or multi-gigabit serial I/O pins?

            o Are there constraints on some signals such that they all must route to the same clock region or to the same bank of the FPGA?

            o What about strobes for memories? They have a specific relationship to the data bits.

            o What signals are already connected to a particular bank? That affects how other signals can be connected to that same bank.

• Where are the components placed on the PCB? This directly impacts the choice of optimal pin assignments, at least from a system perspective. Choices made here impact the time it takes to route the signals to the FPGA and in some cases increases the number of layers required to route the signals.

The value of using a tool like Allegro/OrCAD FPGA System Planner is that it can automatically deal with all of the issues listed above and it can also be used within the Allegro PCB design tools as an "engine" to guide/assist the PCB designer (which is the topic of Part 2 of this blog series).

In the simple example above, if the FPGA on the right has its pin assignments on the left and vice-versa, it's conceivable that the 32 interconnects should be easy to route on the PCB.  But what would happen to the routing if the FPGA placement changes or if PCB restrictions demand that the signals have to be flowed around the FPGA's?   The PCB designer is then either going to have to figure out how to route the board with the original pin assignments or he is going to have to work with the FPGA designer to change the pin assignments to better meet the PCB routing needs.  Or, if he or the PCB tool understood the FPGA well enough to make informed pin swap decisions (see the list of items above that have to be considered in this effort), he could do this immediately, eliminating countless hours of haggling with the FPGA designer.

Several customers have used this approach of planning their FPGA pin assignments while simultaneously assessing the affects of those assignments on the PCB layout -- and vice-versa.  Many of them reported shortening their time to integrate FPGAs with their PCBs anywhere from 40% to 75-80% depending on the number of FPGAs used on the PCB.  Three customers, IN2P3 in France, JDSU in Ottawa, and Verisilicon in China, have shared their experiences using this technique. You can read more about this at http://www.cadence.com/rl/Resources/success_stories/IN2P3_cs.pdf, http://www.cadence.com/rl/Resources/success_stories/jdsu_cs.pdf, and http://www.cadence.com/rl/Resources/success_stories/verisilicon_cs.pdf.

In an upcoming blog I'll take this two-FPGA design into the PCB tool and explore what happens as the PCB designer attempts to route the connections with these pin assignments.

Bruce Riggins

How routing is performed to meet the design intent of designers and engineers seems to be a topic of constant debate. Is manual routing better than automatic routing? Is designer-guided, computer-assisted (IOW auto-interactive) better? What’s the best way to produce the best board design?

To get a perspective from an industry routing expert, I asked David Price (president of DFM, a firm that specializes in providing interconnect routing services to PCB designers worldwide),  for his view on this topic. What follows is Part 1 of a 2-part routing blog series from Dave Price.

This always seems to me to be a straw-man argument, suggesting that there’s something particularly better about how the conductor on laminate was originated, as if how the cake was baked was more important than how it tasted. My experience is that we want to leverage the talent and skills of the designer and engineer to express their design intent as successfully as possible. In this case, it is really the destination that matters and we want to use all tools we can to get there.

The Allegro PCB design process is built upon the constraint-driven flow. Constraint Manager allows the design intent to be expressed as DRC rules that check, report, and confirm that the final routing meets all requirements for performance and manufacturability. At the end of the day, in a constraint-driven flow, if the design intent can be expressed as constraints, and the results satisfy these constraints, then how the routing is created should not matter—it’s a Black Box result.

Good routing needs to meet the constraints, but not all design intent can be expressed as specific constraints. Allegro provides three ways to express design intent in routing: performance and build constraints expressed quantitatively in Constraint Manager, planning and flow intent expressed qualitatively through the Interconnect Flow Planner (IFP), and design intent that can’t yet be expressed in constraints—routing judgments expressed elegantly and artistically in manual interactive routing.

Whether by autorouting, auto-interactive routing, or manual-interactive routing, the final routing wants to be good routing that meets design intent, is manufacturable, and does not impact yield in a negative manner. We want to produce final good routing by the quickest, most efficient, cost-effective means we can. I believe this is by using our best mix of these three approaches. The Allegro PCB Designer is built on getting the design done right the first time by offering a constraint-driven PCB design flow. Constraint Manager ensures that the final routing is good routing.

In this blog series, I will talk about different tools users can deploy from automatic routing to design planning tools to auto-interactive tools to plain and simple interactive etch editing tools. First, let me start with a powerful way to reduce the time to route your boards: autorouting with Allegro PCB Router (previously known as SPECCTRA). Next week, I will talk about how design planning can streamline and significantly reduce your time to get routing done on your boards. I will also talk about new auto-interactive capabilities that are introduced in Allegro PCB Editor and its options in SPB 16.6 Quarterly Incremental Releases (this capability will be shown in an upcoming webinar: Routing  Interfaces Quickly and Efficiently on PCBs (Part 2) on Sept 18.

Autorouting with the Allegro PCB Router (SPECCTRA)

The PCB router continues to evolve to meet contemporary routing and constraint challenges. PCB router works so well because it starts by connecting all signals (100% routed) and progresses to solve constraint conflicts. This algorithm eliminates the common complaint about other routers that remaining unconnects can’t be completed.

The Allegro PCB Router is very suited to all designs from small, less-constrained PCBs to very large, complex, highly-constrained PCBs—it’s very scalable. I start from the expectation that the Allegro PCB Router can route everything on any design until I can identify circuits and requirements that require auto-interactive or manual-interactive approaches. This is contrary to commonly held ideas that the router is used just for the simpler cleanup.

I use the router on the most demanding circuits, when it can solve these. That’s not always—but more often than not. The router capabilities continue to advance to meet today’s designs. It’s capable of true coupled-noise crosstalk control including both same layer and z-axis adjacent layer noise management, real-time relative timing, complex HDI routing, z-axis stub strategies, dynamic pin swapping, achieving challenging topologies, and sophisticated diffpair control. A version of the PCB Router is included in all Allegro and OrCAD PCB Editors, SI, and APD.

I most often route the entire board simultaneously. This makes autorouting different from interactive routing, which is by definition sequential—one circuit, then another. Sequential routing can still be done in the automatic autorouter when needed and appropriate. Key circuits that are especially demanding may need to be routed first. Examples might be DDR2 and DDR3, which I autoroute in the PCB router first. Real estate must be devoted to these so that additional routing accommodates itself to this routing. High-speed differential interfaces are often another example of route first.

Using the PCB router to improve your design process is not an either/or, all-or-nothing approach. There are many supplemental productivity improvements using the PCB router—fast assessments of fanout, placement, layer stackups, and routeability. Setting up and using the PCB router results in repeatability of standardized quality and quick-turn reroutes for ECOs.

I would like to hear from you on what you have tried with autorouters or other approaches to reduce the time to route dense boards (small or large).

Dave Price is president of DFM in Oakley, CA. DFM is a design and consulting firm providing interconnect solutions services to the OrCAD, Allegro, and general PCB engineering communities. DFM specializes in using and applying the Allegro PCB Router (known as SPECCTRA) to complex and highly-constrained designs using the Allegro constraint-driven flow. Dave is also a partner and product marketing director for BornToRoute in Jacksonville, FL, which provides products like MakeDo, MakeCAP, and MakeGood. 

The 16.6 Allegro PCB Editor release provides enhanced Object Filtering to control object display in the Constraint Manager (CM) Worksheet. This feature enables you to select and filter out objects that you want displayed in the CM worksheet.

Read on for more details…

The objects for diff pair model sub-filters are in the same Filter dialog as a tree. The main level of the tree contains existing object types. Sub-filters are available in the tree control as leafs:

 

The "Advanced Filters" pane has three new checkboxes representing “Global,” “Interface” and “Local” objects. The checkboxes are available only in the front-end (Allegro Design Entry HDL– DEHDL) integration of CM. Here’s the Filter dialog:


 

The sub-filters are object-specific and are displayed under the objects they belong to.

Nets of XNets sub-filter controls the Nets of XNets display, is straightforward and represents exactly what you see.

Zero/One Pin sub-filter allows filtering out zero / single-pin nets.

Voltage sub-filter filters out voltage nets (VOLTAGE property set). This sub-filter will be enabled only in the Properties / Net / General Properties worksheet. In the rest of the worksheet it’ll be greyed out and unchecked. It’s a good reminder indicating the “Electrical worksheet is not showing Voltage Nets.”

Model-defined sub-filter will filter-out model-defined differential  pairs.

Library-defined sub-filter will filter-out library-defined differential pairs.

Schematic-defined sub-filter will filter-out schematic-defined objects (only in DEHDL).

Worksheet Presentation

Objects
Is used as a super-header and covers three object-related columns:

Type
The object type.

"S"
Stands for “suffix” or “sub-type.” This column will show “G” for Global objects and “I” for Interface objects (for DEHDL only). The same column includes “sub-types” for existing differential pair “Model-defined” (M) and “Library-defined” (L) objects.

Name
Shows the Object Name.
 

New column for suffixes in the CM UI

Right mouse click on each of the columns to see the options.

For the “Objects” super header the menu contains two items:



 

For the “Type” and “S” columns the menu contains three items:



 
For the “Name” column, the menu corresponds to the pre-16.6 menu for the “Object” column:




As always, I look forward to your comments on using these new capabilities.

Jerry “GenPart” Grzenia

In part 1 of this blog, I discussed a scenario that PCB designers working with FPGA-based boards are often faced with: getting pin assignments from FPGA and/or schematic engineers that can create serious PCB routing problems.  In that blog I claimed that the upstream engineers can't accurately assess the impacts of their FPGA pin selections on the PCB partially because the tools they use don't consider the PCB.  As a result, the team can sometimes spend weeks trying to reach closure on system-optimal FPGA pin assignments.  And I proposed that the solution is to bring the PCB knowledge to the front-end engineers and give the PCB designer the power and knowledge to make valid changes to the FPGA pin assignments.

To demonstrate this scenario, in the first blog I created a simple, two-FPGA design, with an interconnected 32-bit data bus.  In part 2 of this blog, I will take this design into the PCB tool and see what happens as the PCB designer attempts to route it.

Figure 1 - The FPGA designer's PCB placement assumption

If the PCB layout matches what the FPGA designer assumed, the PCB designer should have no problems routing the connections.  But what happens if the FPGAs can't be placed side by side for some reason - maybe another component needs to occupy the space - and the PCB designer needs to place the FPGAs vertically?

Figure 2 - The PCB designer's placement needs

Or maybe the side-by-side placement is fine but there is a hole in the board between the FPGAs, and the signals have to flow into the top of the FPGA on the left.

Figure 3 - A hole that affects the PCB bundle flow

This could not, or may not, have been anticipated when the pins were first being assigned.  Certainly the FPGA designer and schematic engineer wouldn't have planned for it because they are not directly dealing with PCB routing, and neither they nor the tools they use have any in-depth knowledge of the PCB layout.

Now the pin assignments have too many crossovers and don't look so good from a routing perspective.  And in a typical flow, the PCB designer is probably going to be forced to go back to the FPGA designer to negotiate pin swaps, which means the schematic engineer is also going to have to get involved (those "finished" schematics are now no longer finished).

But what if the PCB designer had been involved with the FPGA pin planning from the very start?  What if he could take the FPGA-related subsystem, with the existing pin assignments, plan the placement and signal flows, and then use this knowledge to propose better pin assignments?  What if the PCB designer had the technology, within the PCB tool itself, to use an FPGA-intelligent algorithm that could automatically re-assign the pins based on how the signals enter the FPGA?  Not a static swap matrix that only understands that two signals are part of the same swap group and knows nothing about the FPGA itself, but an engine, running under the PCB hood, like a built-in FPGA expert.

Let's see what could be accomplished by using Cadence's Allegro/OrCAD FPGA System Planner (FSP) engine, within Allegro PCB Editor.

Figure 4 - Using the Allegro/OrCAD FPGA System Planner engine to assign new FPGA pins

By selecting the bundle and using Allegro/OrCAD FPGA System Planner's FPGA knowledge and pin swapping algorithm to reassign the signals on the left FPGA, not only have better (with respect to PCB routing) pins been chosen for the FPGA, the signals have been unraveled, which translates into faster routing on fewer layers:

Figure 5 - FPGA pin reassignment on FPGA U1

The same algorithm could be applied to the FPGA on the right:

Figure 6 - FPGA pin reassignment on FPGA U2

Notice how some signals on the right-hand FPGA tend to occupy the top center of the FPGA. This is, in some cases, to be expected - in this case the pins on the top left quadrant of this particular FPGA consist of power, configuration, and differential pins.  But since the Allegro/OrCAD FSP engine has full knowledge of the FPGA and the device's pin characteristics, it has automatically picked pins that adhere to the FPGA's capabilities.

There is no way that a static swap mechanism can support this level of FPGA knowledge.  Classic pin swapping technology has barely evolved beyond a rudimentary scheme where groups of pins are tagged as being logically and/or electrically equivalent.  For fixed-pin parts, this works fine.  But for FPGAs, the pin usage rules change as the connectivity to the FPGA changes and a simple swap group approach cannot possibly account for this.  Even if it could, to accomplish the degree of re-optimization highlighted above the PCB designer would have had to spend hours manually moving signals one at a time.

Now that the PCB designer has a signal flow and pin assignments that appear to support the actual routing, what does this look like to the FPGA designer, whose tools do not consider the signal flow on the PCB?

Figure 7 - PCB-optimal pin assignments as seen by the FPGA designer

Without knowledge of how the signals would eventually be flowed on the PCB, it is highly unlikely that the FPGA designer would have chosen the pin assignments shown above.  To him, they make no sense - there are multiple crossovers, the "traces" appear to be longer than they need to be, and the FPGA pins don't appear to be well-utilized.  But that is irrelevant.  If the resulting pin assignments work for the FPGA and the PCB designer's needs have been met, the end result will be a more optimal design that will be routable in less time and with fewer layers.

A short video that demonstrates the scenario above can be found here.  Also, I will be hosting a webinar on September 12^th, 2013, where I will give a demonstration and expand on the concepts I have discussed in parts 1 and 2 of this blog, using a more complex design than the example I've used here.  Click here to register for the webinar.

Bruce Riggins

The 16.6 Allegro PCB Editor includes new enhancements to effectively manage shape operations.

Read on for more details …

Shape Expansion/Contraction

The ability to contract or expand an existing shape(s) is available in General Edit Application mode. Pre-select one or more shapes then use the RMB context sensitive menu to access the Expand/Contract command. Use +/- buttons in combination with the value field to incrementally change the shape size.   
1.    Select General Edit Application mode
2.    Hover over any one shape then RMB – Expand/Contract
3.    Set the value for expansion or contraction in the options panel; 10 mils for example
4.    Use the ‘+’ or ‘–’ sign to incrementally change the size of the shape.

Caution – during contraction as the corners reduce, it is possible to convert the chamfered or rounded shape back to an orthogonal rectangle. If you then expand the shape it will not revert back to its original chamfer or rounded corner.

Context menu for expand/contract:

          
Increment controls:

    
                                            

Add Circle - Ease of Use Improvements  

The following ease of use updates were made to commands associated with adding a circle. Relevant commands include Add Circle, Shape Circular and Shape Manual Void – Circular.

Circle creation options -
o    Draw Circle – mouse guided circle creation
o    Place Circle – user guided placement of parameterized circle
o    Center / Radius – place parameterized circle at x,y coordinate

Change Radius of Line Drawn Circle  
Use General Edit Application mode to easily change the radius of an instantiated line drawn circle. Hover over a circle then use the RMB to access the ‘Change Radius’ command.

1.    Add a mouse guided circle …
      a.    Invoke the  Add – Circle command for this step
      b.    Enable the ‘Draw Circle’ radio option:

 
      c.    Make a pick anywhere in the canvas then use mouse movement to control the size of the radius

2.    Place a pre-defined radius circle …
       a.    Invoke the Shape – Circular command
       b.    Enable the ‘Place Circle ‘radio option
       c.    Enter a radius of ‘50’:

         
       d.    Interactively place a few 50 mil circles

3.    Locate a predefined circle …
       a.    Invoke the Shape – Circular command
       b.    Enable the ‘Center / Radius’ radio option
       c.    Enter a radius of ‘100’
       d.    Enter X,Y coordinates of ‘3000, 1500’:

 
       e.    Click the ‘Create’ button to add the 100 mil circle to the location of (3000,1500):

 
4.    Edit the radius of an existing circle …
       a.    Ensure you are in General Edit Application Mode
       b.    Hover over one of the line drawn circles you added in the previous steps
       c.    Use the RMB to access the ‘Change Radius’ command
       d.    Enter a new radius value; 150 for example:

 

Thermal Width Alignment for Xhatch Shapes

A new dynamic shape option aligns thermal spoke widths used for cross hatch shape applications to that of the line widths used for the actual shape hatching. Normally the thermal line width is controlled by the ‘min line width’ property associated with the net. If the property value changes, the thermal width would be updated. A Flex PCB Designer can now set this option and maintain the integrity of the copper hatched region regardless of line width updates forced by the schematic or property overrides.

1.    Consider the cross-hatched shape (below); note the width of the thermals to be 30 mils.
2.    Select the xhatch shape using the shape-select icon  
3.    Use the RMB and select Parameters
4.    Enable the Use ‘xhatch thermal width’ option located in the Thermal relief’ connects tab
5.    Click apply

Thermals (min line width controlled):
    

Xhatch controlled:

 
                     

Please feel free to share your experiences with these new capabilities.

Jerry “GenPart” Grzenia

The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize the pull-down list values for part property editing. Some classification properties require “freeform” values (tolerance, voltage, etc.) and other properties only accept certain values, for example:
“YES/NO”
“COMPLIANT/NON-COMPLIANT”

This feature allows you to specify a set of allowable values for a property.  The allowable values will appear in a pull-down list.  This eliminates human error and promotes consistency and quality in the library.

Read on for more details…

In the ADW DBEditor, select File > Manage Part Classifications. For each property for which you'd like to enable pre-defined values, select the … field in the Pre-Defined Value column:

 

Select the “…” button next to an attribute (as an example, we’ll use the attribute – “ROHS”). ADW looks through the database for this Classification and retrieves all existing values. Add a new pull-down value, “NON-COMPLIANT”, by typing it into the text field and hitting enter:

 

Select the Save icon on the Toolbar.  This will create a new rev of the classification.  Because there are parts using that classification, it will bring up the following dialog:

 


Select “Preserve”.  You will see a dialog showing that each part using that classification is being updated. Next you will be asked to enter a comment in the check-in log.  Do so and select “Apply to All”:

 


Select “Close”.

You have just constructed a set of pull-down values that can be selected for the ROHS property in that classification… look at the “predefined” field of the ROHS property to confirm:

 

As an optional step you could mark the old Classification Obsolete so the Librarians don’t see both Classifications:

 

Open the ADW System Console and type lib_dist. If you don’t run lib_dist, then you will not be able to Obsolete the old classification because there are still parts linked to it:

 

Select Capacitors Fixed [1.0] and select Obsolete with the right mouse button. Select Yes when you see the following dialog:

 

Search for Capacitors Fixed. Sort Search results. Select CDN-CAP-0001 (as an example):

 

Checkout. Select Capacitors Fixed Classification. The ROHS Property should now have a Pulldown as shown below:

 


Select NON-COMPLIANT from the newly created pull-down list. Save, Check in. Add comment, select OK. Select Release and run lib_dist on the ADW System Console:

 



I’m looking forward to your feedback using this new capability.

Jerry “GenPart” Grzenia

Allegro PCB Editor offers drafting and dimensioning features that support electronic design automation (EDA) industry standards that enable you to specify the dimensions of every feature on a board created from the product. This feature gives you greater control over the manufacturing release of your design. The layout editor also enables you to customize the dimensioning process to conform to the manufacturing requirements of your site. Drafting and dimensioning normally occurs in the later stages of the design process.

From the app note mentioned later in this blog, you will learn how to modify several types of dimensions and control their appearance by setting up dimensioning parameters or by editing individual dimensions. In SPB16.5 version of symbol editor and PCB Editor, when you create a dimension, it is saved as a database object. As a result, the dimension becomes associated with the object and gets edited and deleted with the object.

You can watch the video demonstration on dimensioning associability here: Associative Dimensioning

NOTE: If a symbol that has non-associative dimensions in the symbol file is placed on the board, the dimensions remain non-associative on the board.

Enabling New Dimensioning Environment

To invoke the dimensioning environment in SPB 16.5, use any one of the following:

• Choose Manufacture - Dimension Environment
• Run the dimension edit command (Use the toolbar icon)

After invoking the dimensioning environment, right-click to see the various dimensioning commands available in Allegro PCB Editor.

Migrating Dimensions into SPB16.5

When migrating a board with dimensions into SPB16.5, you have the following options:

• The dimensions added in the previous release remain inactive or non-associated with the objects. They cannot be edited or moved. You can use them as they are.
• Remove the old dimensions using the delete command and re-create them using the new dimension environment.
• Add new dimensions to the design.

Dimensioning Commands in SPB16.5

1. Moving dimensions to another class/subclass

To move an existing dimension to another class/subclass, use the Z- Move Dimensions command.

The valid class-subclasses are:

• Board Geometry
  
     o Dimension
     o Assembly notes
     o User-defined subclass

• Drawing Format 
  
     o User-defined subclass

• Manufacturing 
  
     o User-defined subclass

2. Displaying dimension Information

To see dimension-related information, use the Show Dimension command.

This command opens the "show element" form.

3. Modifying dimensions globally

By initiating the Parameters command, you can set the global parameters for dimensioning to the existing as well as future dimensions. This command displays the Dimensioning Parameters dialog.

In the example below, the linear dimension settings are changed globally.

NOTE: If you change the parameters displayed in blue, these changes will be applied to future dimensions only.

4. Modifying instance-specific dimensions

You can also change the instance-specific parameters using the Instance Parameters command. The parameters displayed in blue can be set to a value other than the global parameter for that particular dimension.

For example, dual dimension is added below the primary linear dimension.

NOTE: The instance-specific setting initially shown is the last setting for the selected dimension.

Similarly, you can add tolerance to any dimensioning instance.

5. Deleting Dimensions

To delete dimensions, choose the Delete dimensions command and select dimension. This command dissociates the selected dimensions from the object and removes them from the database.

6. Locking and unlocking dimensions

To fix/unfix the location of dimension text or leader end-point, use the Lock dimensions and Unlock dimensions commands.

7. Moving and changing dimension text

To move the dimension text location, use the Move text command. This command lets you move and place the dimension text to a new location. Similarly, to edit the dimension text, use the Change text command. You can change the text string by entering the new value in the Options tab.

Watch an elaborative video on dimensioning in Allegro PCB editor at:

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:VideoViewer;src=wp;q=Video/Silicon-Package-Board_Co-Design/spbmm/pcb/dimensioning_pcb_designer.htm

Refer to the app note here for the detailed step-by-step procedures on the Dimensioning functionality, as well as various other aspects that are not covered in this blog.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com/).

Naveen Konchada
Cadence Customer Support

The 16.6 OrCad Capture release now allows you to replace multiple cache parts in one operation. In addition, all options of Replace Cache now work on Update Cache.

Read on for more details…

In earlier releases, you could not use the options available under “Replace Cache” for “Update Cache” operations. You now have the option to select multiple parts in cache and replace them in one operation:





Consider the following example. Expand the “Design Cache” folder in project window – there are two listings of 74ALS573:

 

Select both the items listed with 74ALS273and select RMB “Replace Cache”:

 


Select the 74ALS.olb library from Cadence installation hierarchy and select the 74ALS273 gate from it. Press OK. Note that multiple parts were updated using the “Replace Cache” options.



Please share your experiences using this new capability

Jerry “GenPart” Grzenia

• SPICE circuit generation for all IBIS versions
• Support for V-T curves
• Analog simulation of XNets (use Advanced Analysis tools for smoke analysis on bypass components)

Read on for more details …

The Model Editor now supports all versions of IBIS for V-T curves.

Invoke Modeled.exe.

Invoke the IBIS converter from the menu Model > IBIS Translator.

Browse to Database\IBISImport\epcs64.ibs:


Click OK to generate PSpice Model.

PSpice allows you to simulate nets with SI Model assignments in PSpice. Consider the following example circuit:



Select a design from Project Manager and invoke the library setup. Ensure the library setup is correct:

Select pins U1A.16 and U1B.11 and select RMB > Signal Integrity >Assign SI Model:


Assign any output model to the pin:


Open a TCL Command Window in Capture from the menu View > Command Window.

Type in the following TCL command to activate the IBIS netlisting -
SetOptionString IBIS_PINS_NETLIST TRUE

Next, source a TCL file from your hierarchy -
source {$CDSROOT\pspice\tclscripts\IbisToPSpice\tcl\ibisnetlist.tcl}

Create a transient simulation profile Tran.

Generate the PSpice Netlist from IBIS by executing the following command -
::ibisnetlist::run

Run the PSpice Simulation.

Plot V(Mynet).

Create new measurement:


Launch AA for Sensitivity analysis from Capture.

Import measurement.

In the AA TCL Window, enter the following command -
source {<path>\database\SimulatingSI\PspAAProcessDesign.tcl}

Run Sensitivity Analysis.



I look forward to your comments about how you’re using these new capabilities!

Jerry “GenPart” Grzenia

Ever since the I/O Buffer Information Specification (IBIS) committee broke away from the "signal only" mentality and approved the new standard for including power information within the IBIS spec, there has been a lot of buzz in the industry about performing power-aware signal integrity analysis. Effectively this would mean combining both signal and power integrity analysis into one.

But why does it matter? Users that simulate with ideal power and ground probably think they have been getting along okay. And then there are those that are willing to brave into the world of transistor-level models and hand-generated SPICE netlists that have been able to perform a certain level of signal integrity analysis that includes non-ideal power and ground effects.

But what some say has been missing is a system simulation environment that connects interconnect models together across the various fabrics, such as fast and accurate power-aware IBIS models that connect to the non-ideal power and ground planes. And the system simulation cannot stop with just power-aware I/O models. The interconnect models must include signal, power, and ground, as well as the coupling between. Every fabric between the driver and the receiver (chip, package, and PCB) requires power-aware extraction and the hooks to connect to the neighboring fabrics.

Fortunately, such an environment exists today with Allegro Sigrity SI when utilizing the Power-Aware SI Option. Users of this technology can create power-aware IBIS models, extract PCB interconnect models with coupled signal, power, and ground, and connect these models together to chip, package, and connector models. Once extracted and connected, system-level (I/O buffer to I/O buffer) simulation is available that includes all the required effects. This simulation demonstrates performance during conditions where simultaneously switching signals cause power and ground planes to fluctuate from their ideal voltages.

So, to answer the original question as to why "power-aware" is important... Ideal power provides a false sense of security. You may build a product with meta-stable timing and end up spending hours in the lab trying to debug the problem. A little power-aware signal integrity analysis could have identified the problem before the design was built and led you to a solution without all the hours in the lab and the cost and time it takes to re-spin a design.

For a comprehensive demonstration of how simultaneously switching signals on a DDR interface can be accurately "power-aware" analyzed, please watch the 12-minute movie below.

Let us know your experiences using power-aware models versus ideal power models when using signal integrity tools.

TeamAllegro

A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within the cline path, pins, shapes, and flow lines. Useful in just about any PCB application, the display of net names will be extremely valuable for those involved in design reviews or board debug. This feature is enabled by default in all PCB products and does require Open GL to be enabled. The visibility controls for traces, pins, and shapes are available by accessing the Setup > Design Parameters > Display form.

Embedded net names in traces:

             

Embedded net names in pins:


 
                                  
Read on for more details …

By default, the settings to display net names in clines, pins, and shapes are enabled by default. Review the location of the settings - Setup > Design Parameters > Display:



The complete net name will be displayed, otherwise it will not be displayed as truncations can lead to confusion. Open GL must be enabled and the transparency must be set to less than the ‘Solid’ level:

 

The display of text is right reading. The objective is to maintain consistency in the horizontal and vertical directions. The color of the text aligned with Etch subclass colors:

 

Please share your experiences using this great new feature!

Jerry “GenPart” Grzenia

Beginning with the 16.6 Allegro PCB Editor, the environment variable UPDATE_ECSET_REFDES is now the default behavior.

Read on for more details …

Most Electrical Constraint Sets (ECSets) will map based on Reference Designator (RefDes) values. It is sometimes the only thing that is unique for pins in a topology:

 
In this picture, U21 and U44 have the same SI model and the same pin use. So the only way to differentiate them is by RefDes.

This topology may not map the same way if the design is re-sequenced (RefDes re-numbering). The RefDes renaming can be an automatic process for the whole design or done manually for one component.

In order to address this, the environment variable UPDATE_ECSET_REFDES is made the default behavior. It will change the RefDes in all ECSets based on updates in the design.

For example if U21 is renamed to A-1 in the .brd file, the same will happen to any instance of U21 in the ECSets contained in the .brd.

NO_UPDATE_ECSET_REFDES
A new variable, NO_UPDATE_ECSET_REFDES, is added in the 16.6 release to disable the feature described above.
The variable NO_UPDATE_ECSET_REFDES  can be added either at the Allegro command line or in your local env file.

Syntax
Set NO_UPDATE_ECSET_REFDES

Please share your usage of this capability.

Jerry “GenPart” Grzenia

The recent 16.6 QISR-2 for Allegro Design Entry HDL has new capabilities for the Variant Editor.

Read on for more details…

Dynamic Viewing of Variants in the Schematic Editor

A new toolbar and menus have been added for viewing variants:



All available variants for a design are listed. It’s easy to switch between any of the variants as well as base views. Selecting a variant will lead to the annotation of variant-specific information on schematic sheets:

• Properties
• Do not install
  • Option to cross out

Custom Data Included

A complete hierarchical schematic now includes occurrence-specific data and cross-referencer data. The plotting / PDF publishing of any of the variants contains the complete data.

User-defined properties / custom text can be assigned to variant-specific data in the Variant Editor, and the placeholders on the schematics are updated with variant-specific data.

The attributes form displays the variant name in the source column for variant-specific properties:

Schematic Custom Annotations

• Option on DNI components
  • Cross out
  • DNI property
  • All properties visibility

• Color customization
  • Variant-specific component   
  • Variant-specific properties
  • DNI component   
  • DNI cross

When you save a variant in the Variant Editor it generates files specific to each variant containing variant-specific information, and files are used for dynamic display of data in DEHDL schematics. Variant details can be defined at the time of creating a new variant or editing existing variant details:
–    Variant name
–    Variant property name-value to be annotated on schematics
–    DNI property value
–    Variant-specific custom text values





I look forward to your feedback!

Jerry “GenPart” Grzenia

Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups automatically whenever an interface is instantiated or a protocol is created. These switches control the auto-creation of those net groups. Turning these on builds the net groups as the design is created:

Read on for more details …

The default net group size is 64 signals. Protocols or interfaces with signal groups larger than 64 signals would thus have multiple net groups created. Net groups do not have to be auto-created. Other functionality exists to let you create the net groups later.

For interfaces, access to the net groups is via RMB > Configure Connections…
RMB on a net group cell opens a pop-up menu:

• Auto netgroup group affects just that group
• Auto netgroup all signals group wise will create a net group for each signal group
• Auto netgroup all signals of interface will use the default (64) to create net groups (with no regard to the interface’s signal groups)
• Auto netgroup swappable pins operates on the interface and groups all pins based on their swappability
• Auto netgroup swappable pins of group does the same thing but within a given group

You can also rename a net group. To place signals in a new net group, select the signals then use Create and Assign New Netgroup:

Selected signals can be manually moved to a different net group. To do this, select the signals, then LMB to get the drop-down on a cell and pick the net group to which you want to move the signal. Remove a signal(s) from a net group by selecting the blank field at the top of the drop-down:

For FPGA protocols the net groups are accessed through the protocol form. The functionality is exactly the same as for interfaces:

A design can be “net grouped” after the fact even if the Settings checkboxes to auto create the net groups are turned off.

Note: Net groups do NOT have to be created in FSP. The design can be forwarded to Allegro with no net groups and the net groups can be created in Allegro and brought back into FSP:

Parts with interface-level constraints must be defined as a single net group.

Groups of signals that are constrained in FSP (i.e. “same_bank” or “same_clock_region”) should also be defined as a single net group. The reasons becomes clearer when you get into Allegro and attempt to run the auto pinswap routines. The PCB designer can split the bundles as needed. But, the auto pinswap algorithm doesn’t look simply at the bundle; it looks at the constraints on the signals in the bundle. Thus, the PCB designer cannot arbitrarily create bundles from a group of signals with a “same_clock_region” constraint and expect the tools to let him flowplan those signals anywhere he wants, with no consideration to the other signals. That would violate the FPGA rules.


As always – please share your experiences using this new FSP capability!

Jerry “GenPart” Grzenia

Back in the day, when challenged to transfer data faster, we increased the width of the interface from 8 bits to 16 or from 16 to 32 and so on. The wider the bus got, the more challenging timing became. We added strobes for interface lanes to better manage timing, but faster and wider buses added more complexity. Somewhere around 64 bits and 500 MHz (remember PCI-X 533?), we recognized that the trend could not continue.

Today, with the exception of memory interfaces, multi-gigabit data transfers are accomplished through serial interfaces. Transceivers now include complex adaptive equalization that can only be described through software algorithms. To enable simulation, the industry extended the IBIS modeling specification standard to include an algorithmic modeling interface (AMI).

Cadence's Allegro Sigrity Serial Link Analysis is a full-featured serial analysis solution that includes model extraction, topology generation, and system signal-integrity analysis that supports IBIS-AMI. The die-to-die topology is modeled in SystemSI. An impulse response of the channel is convolved with a large bitstream using high-capacity channel simulation, and then the channel analysis results can be compared to industry-standard compliance tests, such as PCI Express (PCIe) 3.0.

Grab a cup of coffee and watch the demonstration of our complete solution that addresses serial link analysis. These simulation results can be compared to PCIe 3.0 requirements using our compliance kit that ships withAllegro Sigrity Serial Link Analysis.

While many signal-integrity engineers focus on final system verification, you can see from the demonstration the advantages of using the serial link analysis technology early in the design cycle. While most would say that an 8.0Gbps channel such as PCIe 3.0 should be implemented in a flip-chip package, this demonstration shows the flip-chip versus wirebond quality differences. Given the results, an enterprising signal integrity team may want to continue tweaking the channel and transceiver in hope that they can implement PCIe 3.0 in a lower cost package and increase profits for their company.

Tell us about your experiences using SystemSI and Cadence Sigrity modeling and extraction technology!

Team Allegro

How much integrity is too much?  If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are also more expensive than necessary and your decap mounting structures have vias in areas that could be better applied for signal routing.  If you reduce the number of decaps, will you have less integrity?  Will your PCB's Power Delivery Network (PDN) performance (and your performance as a designer) be challenged?

Successful selection of the type and quantity of decaps and their placement locations depend on many factors.  Included in the factors are: device switching current, target impedance profiles, capacitance and inductance (ESL) of the decaps, mounting inductance of each decap and device, and PDN inductance between device and decap.  Even with the availability of detailed simulation tools to verify PDN performance, it is often not clear how to make decap implementation tradeoffs.  Pre-layout decisions tend to add more decaps than truly needed. Selection and placement is often based on experience and"best practices".  And while it is easier to remove extra decaps than to add more during post-layout verification, over-design not only adds the cost of unneeded decaps, but may unnecessarily force use of extra PCB layers due to blocked routing channels that need not be blocked.

Cadence Sigrity OptimizePI provides an analytical basis upon which to make decisions regarding PDN design tradeoffs.  Pre-layout guidance is provided for decap types and how many should be placed on the top/bottom of the design and under the devices. This helps to dramatically reduce over-design at an early stage in the design flow, where it can yield the greatest benefit to the overall design.  Post-layout analysis considers thousands of design alternatives in a completely automated manner and provides a short list of optimal decap schemes from which to select the most appropriate tradeoff for your design. PDN performance is maximized while cost, area, and emissions are simultaneously minimized.  Even for designs that have undergone pre-layout analysis, it is typical to reduce decap cost by 15% while maintaining or improving performance during post-layout optimization. For decap implementations that are over-designed from the beginning, the decap cost savings are often 50% or more with the potential for significant PDN performance improvements.

Grab a warm or frosty cold beverage and enjoy a demonstration of Cadence Sigrity OptimizePI. An 18-layer FPGA-based board is examined for which the 1.5V rail of the original design contained more than 120 decaps. This original design is observed to have impedance peaks, corresponding to high PDN noise, in the frequency range where significant energy will exist for typical switching circuits.  SPOILER ALERT: OptimizePI reduced decap cost and improved performance.

You can see from the demonstration how easily design engineers, board layout designers, and power integrity experts alike can utilize OptimizePI to provide analytical guidance for their decap implementations.

Tell us about your experiences using OptimizePI.

TeamAllegro

The 16.6 AMS Simulator (PSpice) release now includes support for multi-core capabilities. There are several runtime options available to enhance the performance of simulation runs.

Read on for more details…

Performance of multi-core capabilties is enabled. There are focused performance enhancements for large designs with complex model instances like MOSFETS and BJT. In addition, I/O performance improvements with significant performance enhancements for large DAT files are included:



Threads

• Maximum number of threads to be used for simulation
  • THREADS = 1 => Single-threaded simulation
  • THREADS = 0 => Use default calculation
• By default, the number of threads is calculated based on device count, number of cores in the machine, and the PSpice license used.
• The default thread count is <= number of cores/2
• A maximum of 4 threads can be used for regular PSpice licenses

Convergence improvement options

• Advanced biaspoint convergence homotopies
• Integration method option
• Node value limiting
• Relative tolerance
• Accuracy improvement options
• Worst-case control independent of RELTOL
• Behavioral sources TimeStep control for sinusoidal functions
• MinStep independent of TSTOP
• 64-bit data accuracy

New PSpice options—biaspoint convergence

• PSEUDOTRAN
  • Bias-point convergence enhancement
  • Used when all other methods (STEPGMIN, STEPSOURCES) have failed
• ADVCONV
  • Enables all convergence algorithms, viz. PseudoTran, StepGmin, and StepSources (ON by default)
• GMINSRC
  • Enables StepGmin from inside of StepSources
• NOSTEPDEP
  • Suppresses stepping of dependent sources during StepSources

Here are three options that give additional control to power users:

• GMINSTEPS
  • Maximum number of steps per iteration of StepGmin
• ITL6
  • Maximum number of steps per iteration of StepSources
• PTRANSTEP
  • Maximum number of steps per iteration of PseudoTran

New PSpice options—transient convergence

• METHOD = [TRAPEZOIDAL|GEAR|DEFAULT]
  • Integration method to be used during Transient analysis
  • Gear is more stable, so more often used in the default mode
  • Trapezoidal is more accurate
• TRTOL
  • Tolerance for integration error calculated during transient analysis
  • A higher value implies more tolerance, so bigger time steps and reduced accuracy
  • Can be useful to jump model discontinuities in case of fast-switching designs
  • Default = 7
• LIMIT
  • Absolute limit on data values calculated in PSpice engine during simulation
  • Can be used in case of overflow errors
  • Can also be useful for convergence failures in some simulations
• WCDEVIATION
  • Deviation to be used for worst-case analysis
  • Default calculation for worst-case delta is nominalValue * RELTOL
  • If WCDEVIATION is specified, it gets modified to nominalValue *

New PSpice options—accuracy

• PROBE64
  • 64-bit probe data
  • Increases resolution of probe
  • Very useful for differential probes
• NOGMINI
  • Suppress GMIN addition across current sources
  • Gives more accurate results for very low current values
• BRKDEPSRC
  • Sets automatic break-points for sinusoidal behavioral sources
  • Useful for long simulations when default Max Time Step is too big

New PSpice options—simulation enhancement

• VT Tables
  • Optional parameter for table-driven behavioral sources
  • Tells simulator that x-axis of the table represents time
  • Run-time settings supports enabling convergence homotopies and configuration without a simulation re-start

As always, I look forward to your feedback!

Jerry “GenPart” Grzenia

The 16.6 release of OrCAD Capture provides a few enhancements in the area of NetGroups.

NetGroup membership is visible in the schematic and the schematic printout:

 


You can assign NetGroups through the Alias dialog:

 

Read on for more details…


Here is an example showing how to make a simple block diagram and using the NetGroup enhancements.

1. Open a design file. Here’s an example of what can be used:

 

2. Place net aliases:

 


3. Place hierarchical pins:

 

 


4. Select Hierarchical Block Amplifier1 and use RMB > Edit Part.

5.  Edit the hierarchical block and place a triangle of lines:

 
6. Exit the Part mode and select Yes to update. The design should now look like this:

 

7. Open the TCL Command Window (Use View > Command Window).

8. Select the Amplifier1 Hierarchical Blocks and execute the following command in the TCL command window:
 

As always, I look forward to your feedback!

Jerry “GenPart” Grzenia

Over the time, jumpers have found their importance in multiple applications. The following blog is aimed to provide more insight on their usage and implementation using Cadence Allegro PCB Editor.

What is a jumper? A wire jumper is typically a short wire used to electrically connect two points. On occasion, a wire jumper is necessary on a single-sided PCB to continue the signal connection over a group of etch traces. The wire jumpers are available on tape and reel, and can be cut and formed to custom sizes with a resistor forming machine.

Creating a Jumper Package Symbol

A jumper is created as a package symbol with the jumper option enabled in the Design Parameter. The jumper symbol must only contain two via padstacks and a refdes label. Optionally, the jumper may contain place bound, silkscreen, and assembly graphical outlines or text.

Note: If a place bound shape is not defined in the jumper symbol, the application will use the jumper symbol drawing extents when the jumper is placed in the design.

Prerequisites

You should adhere to your company's standards for naming conventions as well as any specific manufacturing criteria. For each jumper, you should have the following physical data:

• Lead-to-lead spacing
• Drill size
• Pad size

Defining the Drawing Type

All commands listed here are described in the Allegro PCB Editor and Package Physical Layout Command Reference.

1. Choose File - New and choose Package Symbol

2. Enter a file name in the Drawing Name field

3. Choose Package symbol from the Drawing Type list box, and choose OK

4. Select Setup - Design Parameters

5. Select the Design tab on the Design Parameter form

6. Select Jumper in the Drawing type field of the Design Parameter form, and choose OK

Defining the Via List

1. Select Setup - Constraints - Physical

2. In the Physical Constraint Set workbook, click All Layers

3. Scroll to the right until the column labeled "Vias" is visible

4. Click in the Vias cell

This invokes the form "Edit Via List" as shown below:

5. Double click on a via in the ‘Select a via from the library or the database' field

The via populates the Via List field.

6. If more than one via is listed in the Via List field, then select the newly added via and click the Up button to move the via to the top of the Via List field. Optional elements in the jumper symbol:

While the only mandatory elements in the jumper symbol are two vias and a placeholder for the reference designator you can add additional elements to the symbol, just as you do with regular package symbols, that meet your companies design standards. These elements could be:

• Place bound shape 
• Silkscreen outline
• Assembly outline

Adding a jumper symbol while routing:

The following steps can be implemented to add/place a JUMPER symbol while routing the board file.

1. Select Route > Connect (add connect command)

2. In the Design window, click on the element (pin, via, or etch segment) from which you want to start adding etch

3. Choose the right mouse button Add Jumper selection to add the jumper while routing. Ones that are grayed out either do not exist as a symbol or are not in the PSMPATH

This will place the jumper down at the current location and allow you to dynamically rotate the second via around the first. Once you perform a second pick, the jumper will be instantiated in the design.

Refer to the app note here for the detailed step-by-step procedures on the dimensioning functionality, as well as various other aspects that are not covered in this blog.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Naveen Konchada
Cadence Customer Support