Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables:

–    Netassembler
–    Archiver
–    Purge
–    Packager

It was also less robust with dependencies on external programs, and the error resolution was not always clear.

With the 16.6 release, design migration is more efficient and less error prone. Below is a quick summary of what’s new in ADW 16.6 Design Migration.


Read on for more details …


New 16.6 Design Migration Features and Settings
Command line operation
“Designmigration –help” for full list of options and use

PART_NUMBER synchronization from the Library Flow
<PCBDW_LIB>/distributions/env/libimport_parts.ini file

Directive based migration
The project .cpm file directives can be preserved during migration
<ADW_CONF_ROOT>/<ATDM_COMPANY>/<ATDM_SITE>/cdssetup/pcbdw/MigrateDirective.txt


Running Design Migration

Please share your experience using the ADW Design Migration process.

Jerry "GenPart" Grzenia

Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct and optimized.

Annotation is the automated process of assigning reference designators in Allegro Design Entry CIS, also known as OrCAD Capture. The following AppNote clarifies the fundamentals of the Instance and occurrence modes of annotation in a Capture based design. It explains various aspects of annotation and simplifies the concept behind Instance and Occurrence modes.

What are Instance and Occurrence Modes?

These two modes essentially determine how a design is annotated. The Annotate dialog, as shown in Fig.2, provides the option to annotate a design in Instance or Occurrence modes. The recommended mode of annotation is determined based on the conditions specified in the following table:

Table.1 - Recommended annotation modes

Fig.2 - Annotate Dialog Box

Property Editor

The property editor for any part in a Capture design has a white column and one or more yellow columns. The white column is the instance column and yellow columns are occurrence columns.

Flat and Simple Hierarchical Design

With the above explanation, we can deduce that no part contains duplicate occurrence in a flat or simple hierarchical design. The property editor contains one white and one yellow column for every part and both contain the same value for all the properties. By default, the yellow column is hidden for an INSTANCE mode design. You can click the plus sign to expand the yellow column.

Fig. 3 - Property Editor of a Part in a Flat/Simple-Hierarchical Design

For Complex Designs

The property editor includes a yellow column for each occurrence of a part. If a design contains 3 duplicate hierarchical blocks, for all the parts within that hierarchical block, the property editor will contain one white and three yellow columns.

The Part Reference of parts in yellow columns (at the Occurrence level) must be unique after correct annotation of the design.

Fig.4 - Property Editor of a Part in a Complex Hierarchical Design

In Fig.4, observe that capacitors have four occurrences in the design. C1 has four occurrences, C1, C5, C9 and C13.

Annotation

Annotation is the automated process of assigning reference designators to all the parts placed in the design. Under ideal conditions, annotation must be done as shown in Table1.
However, you can select the desired radio button in Fig.2 for any type of design. So, let's understand what exactly happens when the INSTANCE or OCCURRENCE radio buttons are selected.

Instance Mode

When a design is annotated in the Instance mode, the part reference is assigned/modified in the white column, representing the instance mode, of the property editor.
As a flat or simple hierarchical design is expected to have the same values in the white and yellow columns, this is the preferred mode of annotation for a flat or simple hierarchical design.

Occurrence Mode

When a design is annotated in the Occurrence mode:

• Mostly, the part reference is assigned/modified in the yellow column representing the Occurrence mode of the property editor.
• At times, the Occurrence value for a property may be picked from the Instance column. Such columns appear striped. In Fig 4a, L1 is striped because it is being picked from instance columns while L3 is not striped because it has been assigned at the occurrence level. (See Fig 5) 

Fig 5 - Occurrence mode annotation

Note: As a part will have more than one occurrence in a complex hierarchical design, it is essential that all these occurrences have a unique reference designator in the design. For this, the yellow columns for the parts must have unique reference designator. Therefore, for a complex hierarchical design, the preferred mode of annotation is Occurrence. This ensures that each occurrence gets a unique reference designator.

Controlled Annotation

You can also perform controlled annotation in a multi-page design or a design which contains hierarchical blocks. You can specify the range of reference designator under a hierarchical block or a page. To do this, use the Refdes control required option in the Annotate dialog. Selecting this option gives an additional control to specify range for reference designators as per the hierarchical block or schematic pages.

Fig 6 - options for controlled annotation

For hierarchical designs, you can define a range for each hierarchical block. For flat designs, you can define a range for schematic pages.

Exception in Design Annotation Modes

Sometimes it can be seen that for a flat or simple hierarchical design, the preferred annotation mode is Occurrence. This is the case when any property value has been manually modified in the yellow column (occurrence level). Even adding a space in a property value at the occurrence level will make the preferred mode change from occurrence to instance. In such cases, the preferred mode can be changed using the Accessories > Transfer Occ. Prop. to Instance > Push Occ. Prop into Instance command. Sometimes it can be seen that for a flat or simple hierarchical design, the preferred annotation mode is Occurrence. This is the case when any property value has been manually modified in the yellow column (occurrence level). Even adding a space in a property value at the occurrence level will make the preferred mode change from occurrence to instance. In such cases, the preferred mode can be changed using the Accessories > Transfer Occ. Prop. to Instance > Push Occ. Prop into Instance command.

This will transfer all the yellow column property values (occurrence level properties) to white column (Instance), making both the same and switching the design back to the Instance mode.

Refer the following AppNote for the detailed understanding of these modes in the Capture - Allegro PCB Editor flow.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com/).

Naveen Konchada
Cadence Customer Support

Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS (Capture) product has a few new enhancements for Saving designs.

Read on for more details ...

Save

In the Hierarchy viewer, you’ll now see pages and library components which have been modified by the designer marked with an asterisk (“*”). These are schematics and pages that require saving prior to existing Capture:


 

Save As

This enables a user-controlled save of associated files along with the project at a new specified location while maintaining the original references.

Available options:

• Copy DSN to Project Folder
• Rename DSN to match Project
• Copy all referred files present within the project folder
• Copy all referred files present outside of the project folder

Saved associated files include referred projects, designs, libraries, simulation profiles, output files, etc.

Select Project (Design Resources) and RMB click on Save As:


 

Change the destination directory and project name:

Please share your experiences using these new features.

Jerry "GenPart" Grzenia

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage loses its resolution, displaying staircase waveforms. With 64-bit precision, for the same signal, a perfect ramp waveform is displayed.

Here’s a simulation output with the 32-bit data precision set (notice the staircase style of output):

Now, change the Probe Data option to 64-bit:

Here’s the resulting waveform (notice the smooth results):



I look forward to your feedback!

Jerry "GenPart" Grzenia

Just a very "quick read" on a new option for Quickplace this week.

The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components are placed not to overlap each other. As a result, the application may fail to place components if space is not available. A new control option in the 16.6 release,"Overlap components by," has been introduced to improve completion percentages. You can control the amount of overlap - the default value is seeded at 50%.

Read on for more details …

Invoke Place – Quickplace
Enable the option "Overlap components by," which is located near the end of the form:

 

Set ‘Edge’ = ‘Top’
Click ‘Place’ then review the results:

 

Feel free to provide feedback on this new capability.

Jerry “GenPart” Grzenia

In previous releases, the wire bonding toolset was primarily contained within the “Wire bond Select” command. This allows access to all of the common wire bonding functionality, based on what you’ve selected in the canvas when you press the right mouse button. The goal in the Allegro Package Design (APD) 16.6 release is to provide an application mode specifically for wire bonding. 
              
Rather than running the Route > Wire Bond > Select command to perform common bonding operations, you can now change to the wire bond application mode. This allows the designer to move seamlessly between running a bonding command and any other support command, such as show element, route connect, or even symbol editing. The context-sensitive RMB menu shows the available commands. Once one is selected, you perform whatever actions are necessary to complete that command, after which control returns to the wire bond select idle state.
 
 
Read on for more details …
 
 
Menu Access

The wire bond application mode is available from the menu in the same location as all other available application modes.
 
Setup > Application Modes > Wire Bond Edit:


 
 
Also, with the Wire Bond application mode, you can enter the app mode from the RMB > Application Mode list:


 
 
Or the application mode popup in the bottom status bar of the main canvas:


 
Command-Line Access

The command line to launch the application mode is“wbedit”.


GUI's

At this point, you pre-select the item(s) on which to operate. The RMB menu shows the available commands, and picking one allows you to complete that operation. In addition, if you wish to act on only a single item, there is no need to click to select it first. RMB on the item will automatically select that item and give the appropriate context-sensitive menu. While there are no changes to the individual commands, once an action has been selected inside the application mode, the images below show the standard RMB menus when each particular item type is selected.
 
With Component(s) selected these commands are available with the RMB:


 
 
With Pin(s) selected these commands are available with the RMB:


 
 
With Bond Finger(s) selected these commands are available with the RMB:


 
 
With Bond Wire(s) selected these commands are available with the RMB:


 
 
With Guide Path(s) selected these commands are available with the RMB:


 
With Power and Ground Ring(s) selected these commands are available with the RMB:


 
Quick Utilities menu with global settings and profile definitions:



Please share your experiences with this capability.

Jerry “GenPart” Grzenia

In previous releases, when you extract a net into SigXplorer, all the structures are automatically solved in Allegro PCB SI and then passed to SigXplorer. At times, the layerstack of the extracted structure might differ from the real layerstack in terms of the voids in a plane layer or shapes on the conducting layer. In such cases, the structure needs to be re-solved in SigXplorer. At other times, a field solution in SigXplorer takes a long time to run and often runs when not needed.
The 16.6 release of Allegro PCB SI provides support for on-demand solving of models using Bem2D, Ems2D, and FSVia. However, unlike previous releases, now compulsory model solving during extraction from PCB SI is eliminated. The vias and trace models are unsolved when extracted from PCB SI and no impedance values are reported for trace models after extraction if no matched models are found in the existing working IML library.

Read on for more details …

AutoSolve

The autoSolve parameter, when set to On, automatically calls the field solver when you make changes in the parameters of a trace in the spreadsheet, for example. By default, the autoSolve parameter at the circuit level is set to Off. As a result, during extraction, no solving is triggered except for FSVia. FSVia models are always solved during extraction:


 
For the commands which require a field solution, such as Simulate, Generate S-Parameters, and Transform to Constraint Manager, the default status of the autoSolve parameter is overridden and models are produced.

Solving Models

Models can only be solved using one of the following methods if the autoSolve parameter is set to Off by default -

• Running a simulation
• Using the Manage Unsolved Parts command
• Using the Solve Batch Mode command

The Manage Unsolved Parts command helps you manage all the unsolved parts including vias and traces. This command can be accessed through the Analyze menu or by right clicking in the SigXp canvas -     

Analyze menu:

RMB menu:

The command launches the Unsolved Part dialog which lists all the parts that have not been solved:


 

The Part Name column lists unsolved parts, while the Type column shows the type of the part, such as via or trace. The currently selected solver for vias and traces are also displayed. For example, in the figure above, FSvia will be used to solve the Vias, while Bem2D is used to solve the traces.

Note: All of the parts in the design appear in this dialog if there are no solved models associated with the extracted geometry found in the interconnect model library. If you run the Solver for one of the vias or traces, it is possible that the geometry matches one or more of the other elements. If so, the next time you launch this dialog, it may show fewer parts than expected.

Solving in Batch Mode

You can also solve traces and all vias using the Solve Batch command. Use this command to solve a single part in order to see the impedance, for example, or to create a model in the library with the current parameters.

Right-click on an unsolved part and choose Solve Batch Mode (FSvia):


 

Please feel free to share your feedback on this new PCB SI capability.

Jerry “GenPart” Grzenia

Flexible PCBs are used widely in everyday technology and electronics in addition to high-end, complex completed components. Two of the most prominent examples of flexible circuit usage are in hard disk drives and desktop printers. The following blog highlights the features of Allegro PCB Editor (Allegro) along with the Miniaturization option that provides a routing solution for flexible (flex) circuits.

Flexible Circuit Technology

Flexible (flex) circuit technology is used for assembling electronic circuits by mounting the devices on flexible plastic substrates, such as polyimide or transparent conductive polyester film. As the name suggests, these circuits are flexible in nature and are used in consumer products as well as in computing applications and military equipment.

Some basic forms of flex circuits are:

• Single layer - This construction entails circuits mounted on a single conductor layer made of metal or conductive polymer, over a flexible dielectric film.

• Double layer - In this construction, flex circuits are placed on two conductor layers. Here, fabrication may require to be plated through holes, as needed.
  
  
   
• Multi layer - The construction of flex circuits spanning three or more layers of conductors is known as a multilayer flex circuit. These multiple layers may not be continuously laminated together throughout the structure and may have openings, if needed.

• Rigid flex - This structure is a combination of flex circuits placed on rigid as well as on flexible substrates. These are laminated together into a single structure.   

Board Outline

Flex boards are versatile in shapes. CAD design software, such as AutoCAD®, can be used to create a board outline that can be imported into Allegro PCB Editor. Allegro PCB Editor can import IDX, DXF, and IDF files that contain the outline, cutouts, and other mechanical features that are critical to the design.

                                      CAD to BRD Translation 

Design Guidelines for Flex Circuits

Flexible-circuit designs not only face challenges similar to the ones rigid PCB designs face, but also some additional challenges. The very nature of a flex circuit is in its being able to bend and flex. This makes it as much as a mechanical device as an electrical one. This creates a special set of requirements unique to flexible circuitry.

Understanding how these requirements interact allows a PCB designer to create a flex circuit that balances the electrical and mechanical features into a reliable, cost-effective interconnect solution.

The guidelines used for designing flex circuits using Cadence Allegro PCB Editor are described in the subsequent sections.

Routing Consideration Using Route Keep Out

In general, users set up the cross-section for the maximum number of layers as per the design requirements.

Then a designer adds Route Keep Out areas as required for the cavity between Rigid and Flex or connectors. Included in the stack-up are many user-defined layers to represent the flex cover and masking layers. The designer may add a line or rectangle at the bend areas where traces are required to cross perpendicular.

                         Cover layers for rigid-flex design

An example layout requirement for a multilayer (6 layer) Rigid-Flex design -

        Example Layer Stack-up for rigid-flex design

Top and bottom layers are shield while inner layers are flex layers. There is a stiffener in the middle to strengthen the symmetry. The areas highlighted in red are cavities. It is recommended to place layer restricted Route Keep Out (RKO) in flex board areas to specify the cavity area and make a note for the fabricator on cavity requirements.

                               Route Keepout as Cavity

The designer can use the Z-copy command to copy the RKOs to the other layers where routing needs to be restricted. Placing a connector at the protruding flex Layer 2 or 5 can be controlled by editing the pads associated with the thru hole connector (Use the option of null in the Pad_Designer for the layers that are not relevant.)

Conductor Routing

Flex requires special considerations for routing due to its flexible nature and its versatility in shapes. Below are the routing capabilities from Allegro PCB Editor which can be employed for flex routing.

Multiline Routing

The flex-interconnect path generally spans across the flex section of Rigid-Flex design. The preparation entails testing multiple routes of specific widths and the respective conductor spacing as per the floor plan. Flex circuits mostly undergo potential reroute for the bus.

Using the Hug-Contour Option

Rigid-flex designs require curved bus lines. A flex board outline may also change during the design cycle. The ability to easily adjust the connect lines to the new form factor is critical.

The Multiline routing feature coupled with the hug-contour option lets the designer route multiple lines on the flex portion of the rigid- design in minutes instead of long hours based on traditional routing of one trace at a time.

              Example of multiline route abiding the route keepin as contour

New Slide Functionality for Arc Editing

With v16.6, a new slide functionality has been introduced. The slide command utilizes a move-intersect algorithm that delivers smoother and localized edits. This change simplifies the slide of the off-angle arc routing, and provides new options to improve efficiency. Note: The bubble mode is no longer allowed to wear down the arcs of an existing route.

Auto Interactive Convert Corner (AiCC) command

In v16.6, the Auto Interactive Convert Corner (AiCC) command has been introduced to improve efficiency in converting route corners in the Allegro design. You can interactively select nets, clines, or segments, for conversion to Arc, 45, or 90 degree corners.

Choose Route - Unsupported Prototypes - Auto Interactive Convert Corner.

AiCC can be run on existing Nets, Clines, or Segments

In v16.5, the glossing routine can be employed to convert 45- and 90-degree bends to arcs. It is useful for flex circuits because the resulting arcs may be time consuming to edit manually.

Refer to the AppNote for the detailed procedures on various routing methodologies discussed above, and also various other aspects that are not covered in the blog above.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com/).

Naveen Konchada
Cadence Customer Support

The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that exports to ADS, and also the enhancements for existing layout IFF interface (import and export) to support the generic via exchange.

Layer-to-layer via structures are almost always used in PCB designs. These common structures are not standardized in ADS -- they are represented in several ways. These include instances of via models such as the microstrip VIA2 and as layout-only footprints that define the catch pads and drill holes with simple polygons.

The disconnection between the capabilities of PCB tool via structures, and the equivalent objects in ADS, makes design transfer difficult. A PCB tool via structure must be flattened to simple polygons for transfer to ADS, losing most of the information contained in the original PCB via. Likewise, those simple polygons can be transferred back to the PCB tool, but are not identified as a via structure and not treated as a layer-to-layer connection. ADS does not have the PCB compatible via library, which means there is no padstack definition for a generic PCB via.

To solve the problem, Cadence and Agilent developed a solution -- you can export Allegro generic via padstacks first from the PCB Editor, and then ADS will build a PCB-style via library with the pcbViaLib utility offered in ADS2011.10. Agilent has provided the pcbViaLib design kit, which provides via import utilities and a new ADS component, the pcbVia. This design kit defines a data file format that holds the definition of a PCB-tool style via structure, which is read by the pcbVia component and used with a layout macro to render exactly the same layout footprint in ADS as in the PCB tool.

When you export an Allegro layout design with generic vias to ADS by IFF, you can select export vias as components so all generic vias will be mapped to ADS via components. You can also use the via components in ADS layout and then export the ADS design with the kind of via components by IFF. When importing the design into PCB Editor by IFF, the I/F will automatically map back the ADS via components to Allegro generic via padstacks.

Here is the flow for via management between Allegro PCB Editor and ADS:

 


Read on for more details …

Export Allegro Generic Via Padstacks to ADS

There is a utility under the RF-PCB to export generic vias for ADS via component creation. You can click RF-PCB > Export Padstacks to ADS:

 
All vias used in the design will be listed and then you can select some/all vias to export. Please notice only vias in the layout will be listed on the form, so if you want to export a via padstack, you have to place the via into a design. The via group name is for ADS usage. Once you create the via components on the ADS side, you can place a via component in ADS layout from the specific via group.

Note: It’s best to use a unique group name for each design so that ADS will not get confused. The exporting for via padstacks is not based on IFF format but AEL.

Constructing ADS Via Components

You can only get the required utility in ADS2011.10 or later. If you installed the specific design kit (you need to ask for it from Agilent), you will see this menu in ADS layout:

In ADS layout, click PCB Via Utilities > Import Via/Padstack Group… Browse to the proper .ael file exported from Allegro PCB Editor, then you will create the via components:

Export Allegro Design with Generic Vias to ADS by IFF

For a design with generic vias in PCB Editor like the following:

 
Click RF-PCB > IFF Interface > Export… to get the following dialog:

 
You can click the More options button, then you can see the Vias tab. Two options are available for via transfer mode. By default, all vias will be considered as components to export. You can still change it to Shape for the exporting as before. You can also RMB click on the header bar to select Change all to components as below:

 

If you export all vias as components, then all selected generic vias will be written out as via components in IFF file so that ADS can recognize them.

Import Layout IFF with Mapped Via Components into ADS

Make a new workspace in ADS and make sure the PCBVIALIB design kit is in current workspace. To import the design into ADS via IFF, click File > Import… in ADS layout, and then select the Cadence/PCB option, and browse the proper folder for the source files:

 

You will get the ADS layout will all generic vias converted into ADS via components:

 
If you double click a via in ADS layout, you will see the details for the via component:

Use Via Components in ADS

Once the via components created in ADS, you can export a layout design with generic vias from Allegro PCB Editor and then import the design into ADS by IFF. The Allegro generic vias can be replaced by ADS via components. Also you may directly use those via components in ADS side. Before you add a via component  into the design, you need to know which vias are available. You can click PCB Via Utilities > List Via Groups, all available via names and via groups will be listed:

 
To add a via component into ADS layout, you can directly enter pcbVia at the following field:

 
The following dialog will appear:

 
You may need to change the viaGroupName and viaName and also padTypes. You can get the viaGroupName and viaName by clicking PCB Via Utilities > List Via Groups. For padTypes, you need to manually specify the value.

The meaning of the padTypes is to specify the pad usage on each layer. On each layer there will be a figure (range: 0-7) to indicate the pad usage on the layer. For example, 2 means the pad on this layer is for anti-pad usage. 4 means the pad on this layer is used as regular pad.

The details of the definition for the padTypes are as following:

So when you use the via components in ADS, you need to know the layer number of the original via in Allegro design (when you export the padstack from Allegro).

Export Layout IFF with Via Components from ADS

Export a design from ADS layout by click File >Export…, and select the Cadence/PCB option form drop-down list:

 
Import IFF with Via Components into Allegro

In PCB Editor, click RF-PCB > IFF Interface > Import…, browse to the proper layout.iff file:

 
All via components in the IFF file will be mapped back to Allegro generic vias:

 


I look forward to your comments!

Jerry "GenPart" Grzenia

Just a brief blog today about a new feature in Allegro PCB Editor.

A new net grouping mechanism has been added in Allegro PCB Editor 16.6 called ‘NET_GROUPS’. Essentially, the Net Group replaces the bus object.

 A Net Group is a collection of net objects. Different types of net objects, such as nets, buses, differential pairs, and XNets can be added as members of a Net Group.  A net object can be a member of one Net Group only.

A Net Group can be constructed in the Constraint Manager.

If constraints are defined on a Net Group, the constraints are applicable to all members of the Net Group.  With the introduction of Net Groups, user-defined collections of net objects are now composed as a Net Group instead of a bus.

 

 

The Object Type for the Net Group is 'NGrp':

 

Please share your usage of Net Groups in Allegro PCB Editor.

Jerry "GenPart" Grzenia

The evolution of signal integrity analysis is similar to many electronic design tasks.  First, best practices were followed. Second, analysis tools were used to verify final designs. Then, to reduce design re-spins, what-if analysis techniques were created to drive constraints that could then be verified at the end of the design cycle.

 Because of tight schedules and time to market pressure, there is often little time to circle back at the end of the design cycle when a problem is discovered during the verification phase.  The pressure is on to make sure that analysis done early will identify all potential problems. However, as sophistication in analysis tools increases, the data used in what-if analysis must also increase in sophistication to provide meaningful results during the early design process.

 An example of how sophisticated analysis tools are becoming can be seen in memory interface analysis.  Many simultaneous switching signals on a DDR data bus with a less than ideal current return path can cause noise referred to as simultaneous switching noise (SSN).  To understand the effects of SSN, special I/O (Power-aware IBIS 5.0) and interconnect models (coupled signal, power, and ground) must be utilized by the analysis tools.  The IBIS 5.0 models must come from the memory controller or memory provider.  However, power-aware interconnect models are typically extracted from a completed design.

Design team challenge

This creates a challenge for design teams wanting to explore various strategies for understanding the impact of SSN on their future designs.  Once a design is fully routed, it may be too late to correct a problem and still meet a tight schedule.  To address this problem, the Allegro Sigrity SI Base and Options provides the ability to create example configurations quickly and then analyze those configurations using a variety of analysis techniques – from first order to detailed 3D extraction and simulation.

The following video provides an example of how the Allegro Sigrity SI Base lets you start with nothing and within minutes create sample designs that can be used for early analysis.

As the video suggests, design teams using Allegro can benefit from this early analysis by taking the working sample configurations and copying the module into a design under development.  The result will be a memory interface pre-validated to be DDR compliant from a power-aware perspective.

If you have any feedback on the value of integrated design and analysis technology, please let us know.

Team Allegro

Related stories:

Allegro Sigrity Makes its Debut at DesignCon 2013

What's Good About Allegro PCB Editor Net Groups? See for Yourself in 16.6!

What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New Enhancements! 

The complexity of the designs is constantly increasing and more and more logic is being placed inside hierarchical blocks. This leads to an increase in the number of interfaces that are exposed by the hierarchical block. The increased number of interfaces means more pins are required on the block symbol. In many cases, the block symbols become so big (e.g. FPGAs, large pin count devices) that they cannot be placed on a  standard page border. These large block symbols also become difficult to manage because of the many pins coming out of the same symbol.

The 16.6 Allegro Design Entry HDL release provides a solution to better manage the hierarchical block symbols by splitting them into multiple split symbols. This has been an often requested enhancement! Instead of generating a big monolithic symbol, you have an option to split the ports of the hierarchical block over multiple symbols. This reduces the size of the block symbol. Also, the ports can be logically categorized and placed on different symbols to create symbols that can be placed across schematic sheets, especially near the circuitry to which they connect to. This makes placing the symbols much simpler and managing numerous pins easier.
This functionality is available in the 16.62 release.

Read on for more details …

The Allegro Design Entry HDL (DEHDL) Component Browser now shows a hierarchical block’s split symbol viewing and instantiation:

 

Schematic operations include -

–    The symbol version can be changed using the RMB Menu
–    Cut / Copy / Paste / Delete
–    Moving of split symbols across pages
–    Ascend / Descend Split Symbols
–    Highlight  / Cross Probing


 

There are several Hierarchy Viewer Operations:
–    Display a single entry for each block instance
–    Display a block identifier name (SPLIT_BLOCK_NAME)
–    Selection opened the first page of the block schematic instance
–    RMB Menus
     –    All operations are the same
     –    Select instance lists all split block instance symbols
     –    Selecting an entry navigates to the selected block split symbol


 


To generate a split symbol hierarchical block, you use Genview. There’s a new option to generate split symbols:

 

The distribution of pins across symbols can be done by using the Distribute Pins dialog or via Auto Distribution:

 

 

The Distribute Pins Dialog allows you to –

• Select one of more ports and move them to a symbol
• Contains buttons for main commands
• Provides sorting and filtering
• Has an option to Retain Graphics for each symbol
• Ensure a port exists only on one symbol
• Utilize RMB Menu commands

You also have the ability to use the command line genviewHDL command as well as importing via a text (.csv) file.


I look forward to your feedback on experiencing this new capability!

Jerry “GenPart” Grzenia

• Rules file can be added via the Component Browser as Real Interfaces
• FPGAs can be linked to corporate symbols/footprints
• Virtual Interfaces can be converted to Real Interfaces
• FSP generated symbols can be customized as split symbols
• Pin directions for generated symbols can be customized
• Page borders, ports, etc. can be selected via the Component Browser
• Part placement options

Some aspects of the above features were available in the 16.5 release as well.


Read on for more details…


Rules file added via the Component Browser as Real Interfaces
A rules file (LRF) that is placed into a design from the Library Explorer Interface Rules tab can be converted to a Real Interface. This RMB menu pick will open the Component Browser and allow you to pick the real part from the corporate library. The referenced rules file for the converted part will continue to be the rules file placed from Library Explorer. If FSP can automatically find the mapping file, that file name will be shown in the Mapping File field. If you want to use a different mapping file you can browse to a different one. You can also define the mapping from scratch by clicking on the “Define Mapping” button in the bottom left:




FPGAs can be linked to corporate symbols/footprints
An FPGA placed from FSP’s Library Explorer can also be linked to your corporate FPGA symbols. RMB on the FPGA and select “Link to Schematic Symbol…”. This will open Component Browser to allow selection of the FPGA from the corporate library. Update Instance Footprint… option (above “Link to Schematic Symbol…”) only updates the FPGA footprint from a dra file. It does not result in schgen using the schematic symbols from the corporate library:




Virtual Interfaces can be converted to Real Interfaces
Virtual Interfaced (VIs) can also be converted to Real Interfaces (this is not new in 16.6). But, when converting a VI to a Real Interface, FSP will create a rules file from the VI. You can enter a new name for the rules file or browse for the rules file, but FSP will overwrite any existing rules file (it will create a backup). Entering just a name for the rules file will result in the rules file being saved at the top level of the FSP project. You have to select an existing mapping file (you can also define the mapping from scratch):




FSP generated symbols can be customized as split symbols
A few other tricks to consider when generating symbols. By default FPGA symbols are split by banks. This can result in huge power symbols as there can be hundreds of power pins in large FPGAs. To force FSP to create smaller symbols you can select Customize Symbol on the Symbol Setup form, RMB on the top header row, select “Auto Split Symbol Pins”, and enter a maximum value for the number of pins in a split (note that parts selected from Component Browser cannot be customized since the corporate symbols are used during schematic generation):




Pin directions for generated symbols can be customized
Another thing that can lead to better looking symbols and schematics is to change how FSP/Genview places the generated symbol’s pins on the periphery of the symbol. The default is to distribute NC, bank power, and global power pins around the edge of the symbol. By changing these settings you can get cleaner looking symbols. This is not new in 16.6. The template.tsg file (normally located in the $CDS_SITE/ cdssetup/concept/genview directory) also affects the quality of the generated symbols:



Shematic generation options
16.6 adds and moves a few options for schematic generation. “Skip Unused Symbol Splits” has been moved from the Placement tab to the top level of the schematic generation form. 16.5 uses InOut as the port type for all pins on the top-level hierarchical block. With 16.6 you can force FSP to use the signal’s directions for the port type. The downside is that if the signal direction changes, the top level hierarchical block has to be updated. Schgen can flatten any hierarchical blocks used for terminations and filters. Power symbols can be automatically added to the schematics. Click on the “…” to invoke Component Browser to pick the appropriate power symbol for each rail:




Page borders, ports, etc. can be selected via the Component Browser
“Display Net Name as Instance Pin Name” allows you to use existing corporate symbols, but the pin name on the symbol is replaced with the name of the connected net. “Skip Terminations and Decaps” will force schgen to ignore any discrete power filter, termination, and decoupling caps in the generated schematic. Flat schematics can also be generated. These are harder to manage in the context of a larger design, but some customers demand flat schematics. When picking the page border, Ctap, Input, Output, etc. symbols, clicking on the … opens Component Browser (in 16.5 this used to be a drop-down selection mechanism):




Part placement options
The placement tab adds further controls over the settings defined in the cref.dat file. The page margins are in addition to what’s specified in the cref.dat file’s lowerleft, upperright, and excludearea settings. Component to Component spacing can be used to force Schgen to leave more space between components so that the cross-referencer has enough space for the cross-reference data. The Page Border information file refers points FSP/schgen to the cref.dat file:

I look forward to all your feedback on these new features!

Jerry “GenPart” Grzenia

Allegro Design Entry CIS provides a new feature called NetGroup, which offers an easy-to-use and more flexible method of connecting schematic symbols in complex designs using the concept of bundling and connecting signals/nets.

What are NetGroups

A NetGroup is a heterogeneous collection of nets. A NetGroup can have scalars (wires), vectors (buses), or a combination of both scalar and vector nets. It can also have other existing NetGroups as members. For example, you can collect together a large number of signals on a page of a schematic into a NetGroup. You create an off-page connector and then connect all the signals on the NetGroup to the signals on another page.

Types of NetGroups

In Allegro Design Entry CIS, NetGroups are classified as:

1. Named NetGroup
2. Unnamed NetGroup

Named NetGroup

As the name suggests, to create a named NetGroup, you must define a name first and then associate the NetGroup members. NetGroup members can be scalars, buses, or NetGroups.

A named NetGroup can be used across a design or can be exported to other designs for reuse. Generally, organizations upgrade their designs with small modifications for which they may want to maintain different designs. If any functionality is common across different designs and demands to have the same set of NetGroups, then the export/import functionality of the NetGroup reduces the design cycle considerably.

Where to Use Named NetGroup

If you have a clear idea about bundling of signals, then you can use a named NetGroup. For example, assume there are 100 signals (nets) in a complex design in which 15 signals can be grouped together to provide required connectivity. In such cases, it is appropriate to choose a named NetGroup.

Unnamed NetGroup

Unnamed NetGroups can be created without assigning a name and without assigning members. A system-generated default name is assigned for the unnamed NetGroups, such as @@UNNG, which can be changed later. The benefit of an unnamed NetGroup is that you first create an empty definition and then add signals as required. While you cannot instantiate the associated NetGroup definition elsewhere in your design (or page), you can reference the NetGroup on other pages within the same schematic. 

Where to Use Unnamed NetGroup

For scenarios where there is no idea about the bundling of signals (that is, which signals should be part of the NetGroup and which should not), it would be appropriate to use unnamed NetGroups instead of named NetGroups. For instance, consider that there are 100 nets in a complex design. Since there is no fixed rule as to which nets should be part of a NetGroup, it is a good choice to use an unnamed NetGroup and later add the members (signals) on the fly, as per the requirement, to achieve the desired connectivity.

Comparing Named vs. Unnamed NetGroups

Advantages of NetGroups

• A NetGroup, being a heterogeneous collection of nets, can contain scalar, vectors or, in case of named NetGroups, even other NetGroups providing a flexible grouping of objects
• NetGroups can be used as a block, off-page connector, or as a hierarchal port as convenient

• A NetGroup can be re-used, which saves lot of valuable time creating different designs. This can be done by creating hierarchical parts or using export/import as described below:

  a. Choose Place - NetGroup from tool bar menu

• Likewise you can also import a NetGroup saved from any of the designs (*.XML). Choose Place > NetGroup and click on Import NetGroup and browse the saved .XML file
   

• NetGroups can be transferred from front to back like defined buses on a schematic page. In Constraint Manager, NetGroups are represented as a bus object, as shown in the following figure.
  
                              

NOTE: NetGroups are not supported in the back to front flow.

• In the SPB_16.6 release, a new feature called NetGroup Pin (as highlighted in below snapshot) has been provided to add a NetGroup Pin in a hierarchal block. When you define the NetGroup, one exit point is created that holds the signals for all the entry points. This exit point is referred to as the NetGroup Pin. After adding the hierarchal pin in a hierarchal block, select that block, and from the pop-up menu choose Synchronize Down to generate the corresponding NetGroup Port on the referred schematic page.
  
  

NOTE: This functionality is not present in SPB 16.5 release.

Refer to the AppNote for the detailed step-by-step procedures on using the NetGroup functionality, and various other aspects that are not covered in the blog above.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com/).

Naveen Konchada
Cadence Customer Support

When designing next-generation products, the common theme is"faster, smaller, cheaper".  When that is combined with longer battery life and lower power consumption requirements, the design challenges can be daunting.  And one thing you know for sure, the project schedule is not going to be extended to allow you to overcome all these challenges.

It certainly makes sense that every electronic product designer has a tool that enables analysis of the power delivery network.  While components can tolerate certain fluctuations in power and ground rails, there are limits to that tolerance.  Having planes that are so heavily perforated that they look like Swiss cheese and scraping away at fill areas to make room for signal routing are only going to exasperate the voltage fluctuations.  But when you're under the pressures of "faster, smaller, cheaper", these are the compromises that need to be evaluated.

DC power analysis, also known as IR drop analysis, is commonly the first tool electronic product designers will turn to when facing these challenges.  However, one common complaint has been that the analysis is done at a static temperature.   With the current returning through perforated planes and choke areas (neck down areas) in the plane, the current density and, therefore, temperature, are going to be higher than in other portions of the PCB where these conditions do not exist. So, analyzing IR drop at a static ambient temperature can lead to inaccurate IR drop predictions.  Fortunately, there is a new trend, led by Cadence Sigrity PowerDC, where IR drop analysis is done concurrently with thermal analysis.  This allows the tool to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's PCB.  In addition to electrical-thermal co-simulation, Sigrity PowerDC is now capable of analyzing multi-board configurations.  So products that have memory cards attached can have the full system power delivery network analyzed.

If this sounds like something you would be interested in learning more about, please watch the 11-minute demonstration video below.

We hope you found the demonstration informative. Sigrity PowerDC has been addressing complex power integrity problems for years, and continues to advance as a member of the Cadence Allegro Sigrity Integration (ASI) 16.6.1 product release.

Please do tell us about your experiences with PowerDC.

Team Allegro

Related stories:

Simultaneous Switching Noise Analysis - The Earlier the Better

Allegro Sigrity Makes its Debut at DesignCon 2013

Why Cadence Bought Sigrity - And How it May Change PCB Analysis

• CPM Explorer
  • Viewing project .cpm data
• Progress Controls
  • Locking/unlocking flow steps
  • Manual advance
  • Access controls – who can access flow steps
• Customizations
  • Changing the welcome page
  • Adding a corporate look and feel

• Adding/deleting/changing buttons on the Flow Manager welcome screen
• Changing cosmetics (colors, images) in flowmgr
• Skills required: XUL, javascript, knowledge of CSS (cascading style sheets)
  • Templates provided

• Removing unwanted buttons and menu items
• Adding new buttons to Site Tools Tab

• Changing colors
• Adding a corporate logo

The 16.6 release of Alelgro Design Entry CIS (Capture) has added productivity enhancements to the Find command.

You can now:

• Search for a property with a specific value
• Use regular expressions for matching values
• Use global find and replace for offpage connectors

Read on for more details…


In earlier versions of Allegro Design Entry CIS (Capture/Capture-CIS) you could only search for strings and if they matched in property values. The 16.6 release Find command now has full regular expression syntax while maintaining backward compatibility on search. There are two new menu items added on the search window:


As an example, select the options in the Search toolbar, enable Regular Expression and Property=Value. Enter "D*" in search window and press enter, and you will see search window has returned all objects that had D*:

Now select Property Name=Value from the find options and enter "PCB Footprint=D*" and press enter:

Only objects with this property are returned:


Enable the search option – Regular Expression. If you search for a Part Reference which starts with C or R and has numeric range between 2 to 9, this is the result:

 


Global Find/Replace—Offpage Connectors

Capture now allows replacing names of the off-page connectors globally. This is frequently required when the designer is trying to merge pages from different flat designs into one flat design.

Select Menu Edit > Browser > Off-Page Connectors and Browse the available offpages:

The following list of offpages are displayed:


Open any page in design. Select Edit >Global Replace:


You can enter data as show above to replace AEN with MYOFFPAGE.

As always, I look forward to your feedback on using these new capabilities.

Jerry “GenPart” Grzenia

There have been a few new library level enhancements made to 16.6 Allegro RF PCB Editor—

• New libraries
• Setup enhancements
• DRC removal for netlist re-import
• Discrete library translator enhancements

Read on for more details …

New libraries

We’ve provided two new RF components that existed in ADS:

• VIA2
• SLINO

VIA2 is a special via component in ADS, which is something like Allegro via padstack (but it’s not a padstack structure):

 
SLINO is a stripline component with a special substrate structure:

Setup enhancements

When you select RF-PCB > Setup, there is a new item named Customize in the drop-down list for the Parameter set in the Options tab. This is used to determine if the GUI will be floating or fixed in the Options tab. There are currently three items:

• All
• Autoplace
• Clearance settings

If you check All, then all RF PCB GUI forms will be floating instead of fixed in the Options tab:

 
If you check the Autoplace option in the form above and then launch the Autoplace command, you will see that the GUI for Autoplace will be floating:

DRC removal for netlist re-import

In the past, after you transfered a schematic to layout and completed the RF placement using Autoplace, if you re-imported the original netlist without any changes into Allegro PCB Editor, you would see a lot of DRCs (shape2shape or shape2pin) and you would have to run autoplace again to remove those DRCs. Because the shape nets for RF components are missed during the netlist importing, all RF shapes have a dummy net. This situation has been enhanced in 16.6 to remove the DRCs when re-importing the netlist without any changes.

Discrete library translator enhancements

When translating a Allegro discrete library to ADS, some pin numbers may not be correct in the ADS schematic. For example, when we export the following component to ADS:

 
The result in ADS may be that some pin numbers are not correctly mapped:

This situation was fixed in 16.6.

Please share your experience with these new capabilities.

Jerry “GenPart” Grzenia

Just a very brief post this week on a new AMS Simulator (PSpice) capability.

The AMS Simulator 16.6 release allows you to undo schematic changes after you’ve done a netlist and simulation.

Read on for more details ...

1. Open a design, for example the sample design located in <$CDSROOT>\tools\pspice\capture_samples\anasim\example\example.dsn
2. Open the page and modify the value of RC1 to 12K:


3. Simulate the design.
4. Use Undo to revert the value back, and simulate again.

Please share your experience using this capability.

Jerry “GenPart” Grzenia

The Shape - Add Rectangle command has been enhanced in the 16.6 Allegro PCB Editor release to support cornering options of ‘Chamfer’ and ‘Round’. Control the corner length/radius using either ‘Explicit Length’ values or as a ‘Percentage of the Short Edge’. When adding a rectangular shape, you have the option to interactively draw the rectangle or add parameterized shapes using the new Place Rectangle option.

Read on for more details …

The following steps will introduce you to the parameterized cornering capabilities.


1. Select the ‘Shape – Add Rect icon' or use the menu path Shape – Rectangular:

 
2. Here you’ll see the new cornering options located in the lower section of the Options Panel:


 

3. The default settings are consistent with previous behavior for this command.

• Draw rectangle
• Orthogonal corner option

4. Add a rectangular shape using the following parameters:

   a. ‘Corner’ set to ‘Chamfer’
   b. ‘Explicit Length’ = ‘Trim’
   c. ‘Trim value’ = ‘10’

5. Notes
   a. Chamfer length is computed to be 14.14
   b. Only Chamfer and Round will enable ‘Explicit length; % of short edge:


 

6. Add a second shape by switching the Explicit Length radio option to Chamfer.
   a. Enter a ‘Chamfer value’ of ‘25’
   b. Note - trim length is computed to be 17.68:

 

7. Here you can change the creation method to leverage the new parameterized driven model
   a. Change ‘Shape Creation’ to ‘Place Rectangle’
   b. Enter  ‘Width and Height’ values of ‘100, 100’
   c. ‘Corners’ = ‘Round’
   d. Maintain ‘Chamfer Length’ of ‘25’
   e. Interactively place 4 or 5 shapes noting the sequential behavior of the application:


 

8. Additional example shapes experimenting with the ‘% of Short Edge’ length option.  
   a. The following shapes were added with parameters of 50 and 100:


 


Please share your experience using these new features.

Jerry “GenPart” Grzenia