With the 16.6-2015 Allegro PCB Editor release, the Snake pattern router can be enabled from the context menu of the Add Connect command. This functionality provides the ability to route through hex pattern packages utilizing arc routing, which has been greatly improved compared to the existing prototype pattern generator. Simply enable Snake mode via the RMB and Add Connect will detect a hex pattern pin/via field and dynamically convert to arc routing:

 

Read on for more details …
 
Snake Mode and Options
The Snake functionality is available in the RMB context menu after selecting a net for routing using Add Connect. Once in Snake mode the bubble options under the Option window will be automatically disabled as the route will be dynamically weaved through the hex pattern as you move your cursor through the pin/via field. Selecting a point outside of the pin/via will convert back to standard line mode to continue routing and convert to arc routing once re-entering the pin/via field. This will allow easy transition from arc to non-arc routing when voids exist in the pin pattern:

     
•    RMB – Snake options – Center Single Traces in Channel

 
This option setting will automatically center the route in the center of the channel and as you move through the channel, it will dynamically show what the resulting route will look like. Clicking with the LMB will accept the pattern as you see it:

 
•    RMB – Snake options – Switch Single Trace to other Lane

 
When the Center Single Traces in Channel is not enabled, you have the ability to switch between the nearest or farthest channel for dynamic routing using Switch Single Trace to other Lane:

 
Routing behavior during Add Connect
Once Snake mode is enabled, Add Connect will detect a hex pattern pin/via field and automatically switch over to arc routing, allowing two single routes or differential pair routing in the channel. Starting a single connection will default to the nearest channel, reserving space for an additional trace in the opposite channel using the default same net spacing. As you move your cursor through the pin/via field, it will dynamically show the resulting trace.

Route a single trace in nearest channel:

 
LMB Select the opposite channel and route a single trace in the farthest channel:


Indicating in a direction will dynamically show the expected route path:

        
LMB Select to guide the dynamic route in the route direction:

       
NOTE: LMB Select outside of the hex pattern package pin field will convert back to normal (non-arc) routing, and re-entering the pin field will convert back to arc routing with Snake mode enabled.

Limitations
•    Single route, two routes, or a single differential pair route will be equally spaced in between the pins/vias in the channel. If the constraints do not allow two between routing, you will see traces dynamically highlight, indicating that a DRC error condition exists and an LMB Select to commit the dynamic routes will result in DRCs.
•    Bubble and Smooth options are disabled when Snake mode is enabled.  
•    Routing in an offset channel (single trace) and switching to a center channel route using RMB – Snake options – Center Single Traces in Channel will produce a 90-degree corner at the transition. Improved transition is expected in 17.2.
•    Snake pattern routing will be disabled once an LMB Select is made outside of the pin field and convert back to Snake pattern upon entering the pin field again. To get a predictable bubble result outside of the hex pattern package, we recommend disabling Snake mode.

Some performance impacts have been seen when the routed cline contains a large amount of arc segments or when excessive arc weaving is done inside of the hex pattern package.

Looking forward to your input!

Jerry "GenPart" Grzenia

The Allegro 17.2-2016 release, the largest in the past 10 years, became available in late April 2016. Since 17.2-2016 includes a database change that usually happens with a dot zero release, many of you may be wondering when the right time to migrate to this new release is.

Included below is an overview of the Top 10 reasons to move up to the Allegro 17.2-2016 release, so that you can better understand the value of each of the reasons. This is the first in a series of blogs to help you learn more about these new capabilities in the Allegro 17.2-2016 release and how you can benefit from them. Each week after this series of posts is published, we will peel the onion on each one of the Top 10 reasons.

1.  Advanced flex and rigid-flex design support – significantly shorten your design cycle

Good news for all the PCB designers who have struggled with flex and rigid-flex designs, which are increasingly used in a broad range of electronic devices and products. The Allegro 17.2-2016 release enables several new capabilities for flex and rigid-flex designs to minimize iterations with MCAD and lower the overall cost for flex and rigid-flex designs. 

The stack-up by zones feature provides faster and easier definition of stack-ups for rigid-flex-rigid designs and improves MCAD-ECAD co-design. This new capability also enables material inlays for PCBs that have a small percentage of high-speed or RF circuitry on it. Material inlays can save up to 25% on boards with small RF/high-speed circuitry on them.

Another area of improvement includes extensive in-design rules for flex designs. This release introduces 12 new layers and 19 new finishes for flex and rigid-flex designs. More importantly, users can add new user-defined layers and surface finishes. The new in-design inter-layer checks provide the ability to check geometries between two different layers.  

2.  New concurrent team design capability – work together simultaneously with your team members

Have a tight design schedule? Are you working with a distributed team on the same PCB design project at the same time? With the new concurrent team design capability in the Allegro 17.2-2016 release, you can work concurrently on the same design. By connecting users to a common Allegro PCB database, multiple designers can easily work on the design at the same time, and any changes made by one team member are seen in realtime by all members. The new Allegro concurrent team design feature can shorten routing time by up to 80% for dense and complex designs.

 3. New padstack editor – easy to use and supports many new pad primitives

The new padstack editor will dramatically increase your productivity when creating padstack through a modern, easy-to-use GUI. A wizard-like approach makes it easy to specify all attributes needed to define and specify a padstack. The new editor provides many new primitive padstack geometries to make it easy to create complex pad / padstacks. With this release users can create padstacks with several new primitive shapes like donut shape, rounded rectangle, or chamfered rectangle, to name a few. These padstacks are not only easy to create but also help streamline the rest of the design process. The 17.2 padstack also provides support for route keepout geometry as part of its definition -  objects can be controlled on each layer of the pad structure or on adjacent layers that can extend beyond the begin/end layers. Stay tuned for more.

4. The best backdrill capability in the industry just got better – easily navigate around vias marked for backdrilling

Allegro PCB Designer was the first to support backdrill capability many years ago. Based on customer feedback, we have enhanced the in-design rules for vias marked for backdrilling to make the design process even more efficient. In addition, we are providing better visuals around the vias marked for backdrilling to avoid creating problems / issues in the first place.

5. New cross-section editor - streamlines setting up of design, rules for stackup-related objects

The new cross-section editor provides set up for all the features such as stack-up by zone, dynamic unused pad suppression, and embedded component design. A dynamic graphical image of the stack-up construct is shown in a dockable window as you define the stack-up characteristics. The stack-up image includes functionality to set and show reverse drill direction. Grid-editing enhancements allow you to add layer pairs or a user-defined number of layers. Miscellaneous enhancements include the increase of material character length from 19 to 250, positive/negative tolerance support for each layer, via label customization, controls to prevent editing of layers or values, and support of unnamed dielectric layers above top/below bottom. Much more to follow in a future blog post.

6. Arc aware routing  with advanced contour hug saves time to route on flex designs 

Whether you are doing flex, rigid-flex or rigid PCBs, Allegro PCB Editor’s routing has been enhanced to be arc aware. The enhanced contour hug trace addition saves users time by providing a more efficient method to add routing during Add Connect by following an existing connect line or a route keepin. It introduces a simple canvas-based two-state click use model that also enables shoving of existing connect lines. Transitions between the non-contoured and the contoured routing are smoothed for line or arc corners. You have to try this yourself to see how easy it is.

7. Tabbedrouting - manage impedance and cross talk in critical signals, especially in BGA break-out regions 

Larger pin count devices and shrinking pin pitches are forcing narrower than usual trace widths. This, in turn, means that single-ended and differential pair signals have to meander through the pin fields, sometimes with arcs. To make matters worse, pin fields are full of voids on reference planes, making impedance uncontrollable. By migrating to Allegro 17.2-2016, you can have access to new ways to manage impedance on signals in such areas. You can control impedance by adding trapezoidal shapes on parallel traces, provide tab count and pitch validation, and manage and delete tabs when traces are edited. 

8. Allegro Sigrity, Better Together - Use “Sigrity verified” custom return path via structures in Allegro PCB Editor

Allegro 16.6-2015 introduced six new return path via structures that you can add. With the Allegro 17.2-2016 release, you can incorporate customer pre-verified via structures to save time laying out the design and avoid any surprises during the post-layout verification process.

9.  Ease-of-use Improvements

Making Allegro PCB Editor easy to use is an ongoing area of focus for us. In the Allegro 17.2-2016 release, we enhanced several features to reduce your time designing PCBs, to reduce your mouse clicks, and improve your customization capability. Now you can add customized commands to tool bars, and the Visibility Pane now allows designers to control layer content more quickly and more efficiently. There are several improvements in Allegro Constraint Manager, too.

10. New design rule checks

As with previous releases, we continue to enhance in-design rules in Allegro PCB Editor. In addition to new rules for backdrilling and inter-layer checks for flex and rigid-flex designs, we added new drill DRCs as well as four acute angle detection rules. For drill DRCs, you may recall that a few releases ago, Allegro PCB Editor enabled dynamic pad suppression, and at that time we introduced a new DRC “hole to other objects.” This DRC associated with dynamic pad suppression was only enabled when a pad is marked for suppression. With this release, Allegro PCB Editor allows you to enable drill-based DRCs on holes that have pads on them –  you can set and check for DRCs for padstacks whose pads are not marked for suppression. For angle-based rules we added these four new rules - minimum shape edge to edge; minimum line to pad angle; minimum line to shape angle; and minimum line to line angle.

To help you learn more about these new capabilities in the Allegro 17.2-2016 release and how you can benefit from them, we are launching this blog post series, 10 Top Reasons to Move Up to Allegro 17.2-2016 Release. Each week after this blog is published, we will delve into more details about each of the Top 10 reasons. Feel free to contact us if you have any questions, or would like to schedule a live demo with our technical experts. 

Hemant Shah

PSpice.com is a new user-community web portal that lets designers, partners, and students access materials related to PSpice® analog and mixed-signal simulation and analysis in one central location.

“The PSpice web portal and community is a good resource for any analog or mixed-signal engineer creating an electronic design,” said Makram Mansour, Ph.D., WEBENCH Manager at Texas Instruments. “Within the www.PSpice.com environment, the designer can quickly create a sub-system design using WEBENCH design tools, select from thousands of component models, and easily export the simulation files to PSpice to characterize its performance. In just a few minutes, a designer can have a fully functioning sub-system board design and layout ready for fabrication.”

“PSpice.com is your one-stop shop for information on PSpice,” said Kishore Karnane, product management director, PCB Group, Cadence. “Analog and mixed-signal designers won’t need to search different websites looking for PSpice information anymore.

Read on for more details…

The PSpice.com site provides the ability to –
• Get access to over 33,000 PSpice models
• Access premium resources for subscribed users
• Engage with a vibrant community
• Learn new skills for using PSpice technology

Analog and mixed-signal designers don’t need to search the web for PSpice models, application notes, or design examples anymore. You have one focal point to search for all PSpice related collateral.

In particular, the ability to engage in the user forum with other designers, university professors, students, and Cadence experts and discuss all things about PSpice technology, analog design, simulation models, and tips and tricks can be quite enlightening.

Take advantage of learning technical details about PSpice technology by viewing the many videos available and reviewing application notes.

There are also upcoming events that you can attend in a virtual class setting.

Please take a look at the new PSpice.com site and share your thoughts!

Jerry “GenPart” Grzenia

Cadence Online Support Features

Setting up ‘My Alerts”

 
The My Alerts section displays a count of the new content items added.  This is generated taking into account your notification, search and technology platform selections.

You can click the link to view the list of new content in a search results page.

Use My Support - What's New to explore the new features of Cadence Online Support (COS).

Sigrity 2016

A central page is created to host all the important links to Sigrity 2016 documents. Check out the “one-stop shop” for Sigrity 2016 content

Videos

Application Note

RAKs

Leave a comment below or make use of the feedback mechanism within Cadence Online Support.
Hope you find these knowledge resources useful.

~Jasmine

Why Rigid-Flex?

For nearly all applications, customers continue to demand smaller, lighter, and more cost-effective products. Competitive pressures also force designers to bring these new products to market at an ever-increasing rate. Designers can deploy flexible PCB materials (flex/rigid-flex) to meet challenging form-factor requirements, eliminate connectors, and improve performance.

What New Techniques are Available to Support Complex Rigid-Flex Designs?

Fabricators are ready for your design’s advanced requirements that have driven components onto the flex substrate as well as required multi-layer flex to shrink in size and improve in terms of high-speed performance.

Begin with First-Pass Success in Mind

To minimize wasted time and money, it is imperative to collaborate early with your fabricators to establish a mutual understanding of capabilities, materials, and documentation expectations for your rigid-flex PCB. Design standard IPC-2223C, “Sectional Design Standard for Flexible Printed Boards,” provides information on adhesive material selection and adhesive placement relative to plated through-holes and vias. (See the link at the end of this blog post for more information.)

To improve first-pass success and minimize iterations, designers should include many more design rules to ensure a “correct-by-construction” manufacturing hand-off and final execution. These design rules include inter-layer checks between conductive and non-conductive layers on flex and rigid-flex designs. New tools are available now to make these tasks more automatic and encourage adoption earlier in the process.

Why More Rules? With Flexibility Comes Greater Responsibility…

As always, close coordination with mechanical design (MCAD) will minimize the unexpected problems during the packaging phase of the project. The team can confidently enjoy the flexibility of rigid-flex designs (pun intended) when new rules are included to bridge the MCAD-ECAD domains. Since reliability is key, design rules are typically focused on the degradation of the system in the transition zone and on the flexible substrate. Rules include: minimum bend radius, avoid placing vias in bend areas or transition zones, avoid placing component pads too close to the bend area, and, finally, avoid placing stiffeners that can interfere with the bend radius and are too close to vias and pins.

How Can Allegro 17.2-2016 Improve Your First-Pass Success When Designing with Flex/Rigid-Flex?

We redesigned the Allegro cross-section editor to accommodate many new rigid-flex features with different stack-ups for different technologies. You can now define the complete stack-up inclusive of conductor and non-conductor layers such as soldermask, coverlay, stiffener, and adhesives. You can create, edit, and manage physical zones and assign any stack-up to any zone, including constraint regions and rooms (unbending parts of the flex where vias are allowed). As your design evolves, you can move a part from the rigid area to the flex area and Allegro dynamic zone-aware placement automatically transitions the components to the internal database layer representing the flex outer layer. Previously, this was done with workarounds involving pad edits or use of embedded component technology.

In typical rigid-flex designs, the creation of various masks, bend areas, and stiffeners require special clearances or overlaps of materials and spacing. For this purpose, we have introduced a new inter-layer checks spreadsheet with a configurable matrix of custom DRC rules to ensure you meet the requirements for rigid-flex designs. This spreadsheet provides an actual view of what is being built and allows designers to perform more accurate DRC checks, receive better feedback, and provide better data to the CAD CAM tools for fabrication. Since there are many different materials and rules a PCB designer needs to deal with, it should be easy to enable and specify rules for the combination of layers. With our simple process, you can select two layers, define the DRC type and value, and assign a special DRC error code for easy identification on the canvas.

Conquer Complex Routing Paths 

Flexible circuits frequently have complex routing paths to match the unique capabilities of this technology. With Allegro arc-aware routing, designers can easily route a bus while contouring the complex board outline as well as push and shove traces to match changing requirements.

And Finally: Don’t Forget the Allegro Technology Fully Supports Using IPC-2581

Rigid-flex designs are unique when transferring the design data to the fabrication process. The various build-up of materials that make up the final product must be clearly defined, especially for impedance control or complex flex/rigid-flex designs. To confidently communicate build intent, PCB designers now use IPC-2581 to exchange stack-up data electronically. IPC-2581 is an open, intelligent, neutral design data exchange format well supported by PCB design and fabricators worldwide. IPC-2581 revision B now supports bi-directional exchange of stack-up data to eliminate discovery of problems late in the design hand-off cycle.

As always your comments are welcome!

How have you used rigid-flex in your designs?  What are your top three tips to share? Please sign-in above and start contributing to the community discussion.

We will be posting new reasons to "Move Up to Allegro 17.2-2016" shortly!  Please remember to use the "Subscriptions" box at the top of this page to subscribe to this "PCB Design" blog to get updates.

Related Videos

Check out this Allegro rigid-flex design demo video:

(Please visit the site to view this video)

Related Links

10 Top Reasons to Move Up to Allegro 17.2-2016 Release

Cadence Allegro Rigid-Flex Overview on Cadence.com

IPC-2223C, Sectional Design Standard for Flexible Printed Boards (ISBN 978-1-61193-026-9)

IDX News from Printed Circuit Design & Fab Magazine

IPC-2581 Consortium Website

By default, the top and bottom stackup layers do not support the placement of embedded components. When an attempt is made to change ‘Embedded Status’ to either ‘Body up’ or ‘Body down’, the system will prompt you accordingly. To help facilitate the requirement for placing components between the top and bottom layers, the 16.6 Allegro PCB Editor release now supports the placing of components directly on the dielectric layer. This requires you to name the dielectric layer(s) prior to invoking the ‘Embedded Layer Setup’ form.

Let’s explore a couple of methodologies involving named dielectric(s).

Open an Allegro .brd file and then open the cross-section editor - Setup – Cross Section.

Enter a name for the dielectric layer; ‘DK_EMB’, for example:

Open the Embedded Layer Stackup Form ( Setup – Embedded Layer Setup) and set the ‘Embedded Status’ of the dielectric layer to ‘Body Up’. We will not offer a choice of attach methods:

The ‘Embedded_Placement’ property with value of ‘Optional’ has been pre-assigned to the 10 Caps. It’s possible to route on a named dielectric layer. The ‘Allow_Etch’ DRC should be set to ‘False’ to prevent accidental routing from occurring. Set this at the PCSET level:

Enter Placement Edit Application mode.

Window-select several Caps, then use the RMB – Place on Layer command to drop all components to the dielectric layer (consider using the new 16.6 lasso function to make your selection):

Open the Color Dialog – Embedded Geometry folder, noting the subclass structure in place for the named dielectric layer:

Let’s assume the routing strategy includes the use of microvias from either surface to the dielectric layer. Open the BB Via form - Setup – BB Via Definitions - Define BB via and enter information as shown in the figure below, then click OK:

Ensure the ‘Default’ Physical CSet includes these two vias:

Invoke Route – Create Fanout with via direction = ‘via in pad’. Select via BB3-D to connect the 2 pins at the base of the component to the Bottom Layer. Adding a via from the top to the embedded Dk layer will result in a DRC (Via Keepout):

Fanout Settings

Via in Pad

3-D View

Let’s explore an alternative methodology using multiple dielectric layers, as we wish to support the following embedded stackup:

Open an Allegro .brd file. Make the following cross-section changes:

• Add Dk Layer and thickness – ‘DK_EMB1’ = ‘2 mils’
• Edit thickness - UNNAMED DIELECTRIC = ‘60 mils’
• Add Dk Layer and thickness – ‘DK_EMB2’ = ‘2 mils’

Open the ‘Embedded Layer Setup’ form - Setup – Embedded Layer Setup and enter ‘Body Down’ for DK_EMB1 and ‘Body Up’ for DK_EMB2:

The property ‘Embedded Placement’ with the ‘Optional’ value has been pre-assigned to the Caps. Adjust color settings for the two ‘DK_EMB’ layers as you desire:

Move the Caps using the RMB – Place on Layer command. Target both dielectric layers for final placement:

View the board in 3-D. Enable the visibility of placebounds for Top, Bottom and Embedded Packages.

I look forward to your experience using this capability.

Jerry “GenPart” Grzenia

When using the Add Connect command in the 16.6 Allegro PCB Editor, the active layer field will now automatically synchronize to that of a single visible layer. Previously, any visibility adjustment to limit the display to a single etch layer would typically require an additional adjustment to the active layer setting.

Invoke the ‘Add Connect’ command. Disable the visibility of all etch layers:

Enable the visibility of only one layer noting the active layer behavior in the top section of the options form (single-layer synchronization):

Please share your experiences using this new capability.

Jerry “GenPart” Grzenia

New Model Management capabilities are now available in the SPB 16.6 Allegro Design Workbench (ADW) release.

The new model management capability involves creating an environment that manages new model types for the PCB Librarian and other model editors. The benefits:

• Enhance the 16.6 SI DM Model flow for ease of use
• Create a new generic adapter to support a file system based model type
• Create a new generic model browser for model selection to support Copy and Copy As

Librarians create new models using copy or copy as from disk.  The Library Flow supports a generic model browser for a new model to support this use model. This allows the librarian to create a model from either a copy or do a Copy As, at the time of entering the metadata of the model in DBEditor . This capability has been added generically to all existing and new models in ADW. This feature eliminates the need of copying the model to the librarian’s work area after entering the metadata.

Select File > New > Model > Footprint Model from DBEditor:

I look forward to your feedback.

Jerry “GenPart” Grzenia

The 16.6-2015 Allegro PCB Editor release introduces a few new features that provide a persistent capability.

Read on for more details.


Persistent Snap Overview
As an update to the previously added Snap feature, Allegro PCB Editor now features improvements on the popular feature by including Persistent Snap functionality. Users who wish to maintain a specified snap and/or selection type throughout an Allegro session can now do so by enabling the “persistent” toggle option available in the RMB menu of the respective commands.  

Persistent Snap Options
o    Segment vertex - The pick point snaps to the nearest vertex of any of the supported object types
o    Segment midpoint - The pick point snaps to the nearest mid-point of the supported segment type
o    Segment - The pick point snaps to the nearest point on the segment
o    Arc/circle center - The pick point snaps to the center of an arc segment or a circle
o    Symbol origin - The pick point snaps to the origin of the symbol
o    Pin - The pick point snaps to the nearest pin
o    Via - The pick point snaps to the nearest via
o    Figure - The pick point snaps to the nearest figure
o    Intersection - The pick point snaps to the intersection of the segments
o    Off-grid location - The pick point directly returns without snapping
o    Grid point - The pick point snaps to the nearest grid point
 


Snap pick to – Enable the “Persistent snap” option, then select an element type. A check box will appear once the element is selected.

Persistent Select Options
Persistency also now applies to the section options. Allegro PCB Editor now includes Persistent Select. Simply RMB anywhere on the canvas and select Selection Set > Persistent Select and choose the selection type (polygon, lasso, or path). The method of selection will be maintained until such time as you turn it off:



Funckey Key Support
The use of functions keys allows for Persistent Snap types to be turned on or off. Simply click the respective assigned function key to initiate the action before placing components or performing other tasks. The command begins and ends with double quotations. A single quotation follows the snap mode command. A semi-colon exists after the pre-popup command. See below on how you can learn and extract the command(s) that you can then copy between the semi-colon and the last double quotation mark in order to create other function key commands. Here are a few examples:

• funckey p "prepopup;pop dyn_option_select 'Snap pick to@:@Persistent snap@:@Pin'"
• funckey i "prepopup;pop dyn_option_select 'Snap pick to@:@Persistent snap@:@Intersection'"
• funckey c "prepopup;pop dyn_option_select 'Snap pick to@:@Persistent snap@:@Arc/Circle Center'"
• funckey o "prepopup;pop dyn_option_select 'Selection set@:@Select by Lasso'"

Did you know– The command window can be used to echo back command statements like the examples above. Type scriptmode +e in the command window to echo back commands. Copy and paste the echoed commands into your ENV file.

I look forward to your feedback!

Jerry “GenPart” Grzenia

Who Are They?

• Istvan Novak– Senior Principal Engineer at Oracle
• Kevin Roselle– Senior Staff Engineer at Qualcomm
• Stephen Scearce– Senior Manager of High Speed Design at Cisco
• Dale Becker– Chief Electronics Packaging Engineer at IBM
• Ken Willis– Product Engineering Director of High-Speed Analysis Products at Cadence

What to Expect?

East Coast engineers won’t have to travel cross country to hear these regular speakers at DesignCon. We invited five industry experts who work for top tier companies in their industries to speak on interactive panel at CDNLive Boston (session SIP105).

Join us to hear about the challenges faced by these experts as they plan their product designs for next generation cutting-edge technology. Time will be allocated for the audience to interact with one or more of the experts. Bring your questions that only an expert can answer!

The opportunity is limited, register now!

When and Where?

Join us on August 31, 2016 
Boston Marriott Burlington 
Burlington, MA 

Check out the agenda and details.

Who?

Istvan Novak - senior principal engineer at Oracle

Kevin Roselle - senior staff engineer at Qualcomm

Dale Becker – chief electronics packaging engineer at IBM

Stephen Scearce– senior manager of high-speed design at Cisco

Ken Willis - product engineering director of high-speed analysis products at Cadence

What?

Our experts got together and agreed on a set of kickoff topics. These are issues that they are either currently facing or that are lurking on the horizon. The kickoff topics include:

• DC-DC converters – it’s a love - hate relationship
• AMI models for memory interfaces: single-ended signals need equalization, too
• DDR4-3200 – even the most experienced engineers can trip on this max speed interface
• System serial link compliance when utilizing multiple suppliers (chip, package, board, connector) 

Interactive?

Yes!

Time will be allocated for the audience to interact with the experts.

So don't miss the opportunity to listen, learn, and get their perspective on your tough technical challenges.

Space is limited, click here to register, now!

When and Where?

Join us on August 31, 2016 

Boston Marriott Burlington 

Burlington, MA

Click here for agenda and details.

Speakers’ Bios

Istvan Novak

• Senior principle engineer at Oracle
• 20-plus years of experience with high-speed digital, RF, and analog circuit and system design
• Expertise:
  • Signal integrity design of high-speed serial
  • Parallel buses
  • Design and characterization of power-distribution networks
  • Packages for mid-range servers
  • Fellow of IEEE for his contributions to signal-integrity and RF measurement and simulation methodologies

Kevin Roselle

• Senior staff engineer in the corporate Power and Signal Integrity Group (PSIG) at Qualcomm
• Chief technology officer at Bayside Design, Inc., a high-performance interconnect design and analysis consulting company
• Founding engineer at Chip2Chip, which later became Velio Communications, Inc. At Velio, Kevin directed work on several multi-gigabit SerDes and switch-fabric chips in packaging, PCB-level design, and channel analysis. 
• Senior member of consulting staff at Cadence, where he worked on the SPECCTRAQUEST and SigXplorer tools 
• Worked at Digital Equipment Corporation in several roles as signal integrity consultant and in field solver software development
• MTS at Bell Laboratories in Holmdel, NJ, where he worked on small telephone systems design
• BSEE with High Distinction from the University of Nebraska
• MSEE from the University of Michigan

Dale Becker

• Chief electronics packaging engineer for the IBM POWER and System Z Enterprise Systems
• B.E.E degree from the University of Minnesota
• M.S.E.E. from Syracuse University
• Ph.D. from the University of Illinois at Urbana Champaign
• Expertise:
  • Designing the high-speed channels to enable the computer system performance and the power distribution networks for reliable operation of the ICs that make up the processor subsystem
  • General chair of the IEEE EPEPS 2016 Conference and the co-chair of the 2016 IEEE EMCS embedded conference on SIPI
  • Over 25 patents on electrical design of computer systems and has presented over 75 papers in refereed journals and international conferences covering many aspects of electrical computer system design, including power distribution analysis and design and modeling of signal and power distribution networks
  • Member of the IBM Academy of Technology
  • Fellow of IEEE
  • iNEMI Technical Committee member
  • Member of IMAPS and SWE

Stephen Scearce

• Sr. engineering manager in the Central Hardware Group PDS Signal Integrity team (CHG-PDS- SI) for Cisco. This team supports system and silicon high-speed design for Cisco’s ENG Routing, Wireless, Cable, and Security products. 
• Expertise / primary focus areas:
  • ASIC/system power integrity (DC, AC, transient)
  • ASIC packaging
  • SerDes design/analysis
  • High-speed memory design/analysis
  • Worked for Cisco for 15.5 years in the SI and EMC field
  • Worked for NASA in the Electromagnetic Research Branch HIRF team
  • 5 US patents
  • BSET and MSEE from Old Dominion University, Norfolk VA 

Ken Willis

• Product engineering director of high-speed analysis products at Cadence 
• 25 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits
• Prior to Cadence, held engineering, marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity

Lots of documents are posted on Cadence Online Support on regular basis. Let us take sneak preview of recently published documents. You can access the database by logging onto http://support.cadence.com.

Rapid Adoption Kits (RAK)

Allegro PCB Librarian XL Tutorial
This tutorial will guide users through a tour of developing library data utilizing PCB Librarian XL. You will review symbol development and the associated informational views as well as Allegro footprints as part of this material.

Constraint Manager Net Class-Class Constraint Set Assignment Matrix
This RAK demonstrates the process for establishing spacing rules between net classes using the new CSet assignment matrix in Constraint Manager.

SiP Layout Auto Connect
This RAK is intended to provide instruction on the advantage of SiP Layout Auto Connect. The intent of the auto connect feature is to reduce design cycle time for both feasibility studies and product designs by reducing the time it takes to hand draw traces (clines or connect lines) of the logical interconnect.

Application Notes

Allegro Design Workbench: Optimized Library Flow Tutorial
The default library flow in ADW is divided into different Model types. Then, there is a New and ECO sub flow for each model type. There is a great deal of overlap in the New and ECO Flow. This document discusses a New Library Flow called the Optimized Library Flow. It combines these two sub flows into a single flow. It also adds some additional capability to allow you to easily import models created by third party vendors. This tutorial will highlight the changes in the flow and several library related tasks.

Allegro Design Workbench : Part Validation
One of ADW Library Workbench's function is to automatically run a check between the Part Number, the Schematic Symbol and Footprint to verify that the Symbol and the Footprint are compatible. This will be referred to as the Front-To-Back check (FTB), and the utility is con2con.exe. This validation can only happen when there is a Part Number linked to (associated with) a Schematic Symbol and a Footprint. When con2con runs, it performs all the checks in memory, which means that a Schematic and Allegro Board file are never output.

How to Create Laminate RF Symbols from GDS Data
This Application Note describes a process for creating Laminate RF symbols from GDS files using SiP Layout.

Videos

Creating Fillets for BGA Package Configuration
This video explains what a fillet is and it's importance. Video then shows steps to create fillets.

Troubleshooting articles

You can access recently published troubleshooting articles by clicking Here.

Training Bytes:

Self-learning videos to learn more on the tools can be seen from Training Bytes. New videos have been published for:

• Allegro Design Entry HDL
• Allegro PCB Editor
• Sigrity Power and Signal Integrity

Leave a comment below the blog post, or make use of the feedback mechanism within Cadence Online Support (that looks like the image below).

Feedback on any of artifact can be given by making use of “Feedback” form which is generally shown at the top of the collateral.

Hope you find these knowledge resources useful.

Jasmine

Use teamwork to get off the critical path!

When (not if) change happens or scope creeps... the PCB design team is always on the critical path. You can answer this schedule challenge by dynamically scaling resources with the new concurrent team design capabilities in the Allegro 17.2 2016 Release. We created this product offering to provide designers with a quick an easy way to share a common Allegro database to perform collaborative design activities to tackle today's design challenges. Whether a formal project team is formed or at a moment's notice, a designer can simply share their current design and invite other designers to join for assistance. You can also accelerate the project by letting your experts contribute by specialty.  With no added design management by copying databases around and cut/paste design updates into a master database, the newAllegro® PCB Symphony Team Design Option is a real-time collaborative environment using a single database that can be made available to the design team in minutes.   

Solution One:  Think "24 x 7"

Ideal for distributing the work across multiple design locations, our original"asynchronous" Allegro PCB Team Design Optionsupports splitting the work into partitions of the design and merging the results into a master database.  The workflow manager provides partitioned section status and multidirectional communication features that encourage strong collaboration between designers.  Team members can view the work of others and easily address the shared areas between partitions using soft boundaries to work outside of partitions and create layer-based partitions.  The Merge Wizard automates steps involved with front-end netlist changes and automates the merge-import netlist-split process while resolving constraint conflicts.

Solution Two:  Think "Triple Team" (new for 17.2 2016)

Ideal for adding more team members in the same location, our new "synchronous" Allegro PCB Symphony Team Design Option supports real-time co-design.  By connecting users to a common Allegro PCB database, multiple designers can easily work on the design at the same time, and any changes made by one team member are seen in real-time by all members.  The initial release is focused on reducing the PCB design cycle time during the routing stages of the design that can account for up to 80% of the overall project schedule for dense, complex designs.  We provided support for component rearrangement including Reuse Module and Place Replica groups; interactive routing with dynamic shape/trace plowing; route finishing tools like Auto-Interactive Phase/Delay Tuning, Timing Vision and Custom Smooth; and even the ability to complete silkscreen and assembly cleanup.   All users’ modification will generate a temporary display of possible updates with visual "color-coded" canvas locks with each client having the ability to apply permanent locks on interfaces they are working on all to allow the team to work happily.

Save time, get ahead of schedule

Designers today spend the majority of their time during the routing phases of the design and have adopted the Auto-Interactive capabilities to accelerate routing and tuning.  Using the new Symphony Team Design Option in the Allegro 17.2-2016 release, will take it to a higher level with designers working together on the same design to complete the routing effort which can shorten routing time by up to 80% for dense and complex designs.

As always your comments are welcome!

What barriers have you faced bringing multiple PCB designers into one project?  What are your top three tips to share?  Please sign-in above and start contributing to the community discussion.

Related Links
10 Top Reasons to Move Up to Allegro 17.2-2016 Release

What’s New in Cadence^® Allegro^® 17.2-2016

Cadence^® Allegro^® TimingVision™ Technology

Customer inputs are key to product improvements

I can read your minds as you digest the features and benefits of our Allegro 17.2-2016 Release. “Oh no, what have they done now to disrupt my environment?” If you have been an Allegro user for many years, you know what I’m talking about. Dot Zero releases as we call them are our chance to make database / schema changes that result in some level of migration disruption. 17.2 effectively is your dot zero release as it combines the content from the Early Access Program 17.0 software with that of 17.2. Years ago when we wondered what projects to consider, the answer was found in our Customer Change Request (CCR) database that many of you contribute to. While we process many CCRs and often you do not like our immediate response of “Inactive”, please do not take that to mean “Ignored”.  This is the case with the project we called “Padstack Overhaul.” In an aggregate sense, there was no greater number of CCRs in our database than ones related to the padstack. Our decision to take on this project was easily justified.

The project began with database mining, reviewing the 100’s of CCRs about the topic. Our applications team in parallel began work on a new look user interface. Sorry to report your pad related scripts will no longer work, this is the sacrifice we had to make to move our product in the forward direction. Rest assured your 16.6 pad library is compatible with 17.2 if you decide not to leverage any of the new functionality but I think you will like what I am about to share.

The key themes to the improvements are increasing productivity in the PCB design process and improving ease of use.

You asked for it: New Primitives with an Easy Interface

The new editor provides many new primitive padstack geometries to make it easy to create complex pad / padstacks. With this release users can create padstacks with several new primitive shapes like donut shape, rounded rectangle or chamfered rectangle to name a few.

Designers also have parameters to control the corner types on the rectangles which allows you to create tombstone pads or single corner chamfer only. The benefits to your library department will be realized immediately as they no longer need to draw these pads as shapes.

The new Padstack Editor will dramatically increase your productivity when creating padstack through a modern, easy-to-use GUI. A wizard-like approach makes it easy to specify all attributes needed to define and specify a padstack.

You asked for it: Built-in Keepouts

The padstack supports a built in route keepout as well as a field for an adjacent layer keepout. Use the standard keepout geometry for your non plated holes and even the middle layer of an HDI Skip Via. The adjacent layer keepout field can be used to void out planes under surface mount pads to control impedance but also used for mechanically drilled buried/blind vias to prevent shorts when drill overshoot occurs. With adjacent layer keepouts, the librarian generates the geometry while the PCB Designer applies a property to control the number of adjacent layers. (Max is 8)              

You asked for it: Drills

Most CAD systems support a drill field and we come to know this as the finished drill size, the size after plating. But of late, there is demand to support what we call the Drill Tool Size and the Backdrill Size. The Drill Tool field can be used to specify the drill tool you want your fabricator to use. Most likely the usage scenario falls into specifying drills for solder-free pressfit-pin/compliant-pin connectors.

The backdrill field drives a major upgrade to our backdrill application, a topic for another blog. Use this field to specify the backdrill tool size. This information is output to the NC Legend charts. Counterbore and Countersink structures are also supported though not as popular as the requests for the other drill types.

You asked for it: Complex Mask Schemes

Multiple shapes can now be used for mask Layer definitions. The multi-shape mask scheme must be created as a flash symbols (.fsm file) and assigned in the mask pad layer definition. Window pane mask schemes are one example that can benefit from this enhancement.You asked for it: Enhanced Dynamic Shape Properties

I think the most popular Customer Change Request I have come across is addressed with this enhancement. It is now possible to control your pin/via thermal/clearance parameters as they relate to dynamic positive shapes on a per layer basis.   Similar to the use model we developed for creating Constraint Regions, you have the option of applying properties hierarchically; this includes Outer Layers, Inner Plane, and Inner Signal as well as individual layers. The common request I hear is related to controlling the number of thermal contacts on component pins.

As always your comments are welcome!

What are your top three tips to share? Please sign-in above and start contributing to the community discussion.

Related Videos

Padstack Enhancements Demo Reel

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Related Links

Back to “10 Top Reasons to Move Up to Allegro 17.2-2016 Release”

Related material on "What’s New in Allegro" on Cadence.com

The Allegro 17.2-2016 release, the largest in the past 10 years, became available in late April 2016. Since 17.2-2016 includes a database change that usually happens with a dot zero release, many of you may be wondering when the right time to migrate to this new release is.

Included below is an overview of the Top 10 reasons to move up to the Allegro 17.2-2016 release, so that you can better understand the value of each of the reasons. This is the first in a series of blogs to help you learn more about these new capabilities in the Allegro 17.2-2016 release and how you can benefit from them. Each week after this series of posts is published, we will peel the onion on each one of the Top 10 reasons.

1. Advanced flex and rigid-flex design support – significantly shorten your design cycle

Good news for all the PCB designers who have struggled with flex and rigid-flex designs, which are increasingly used in a broad range of electronic devices and products. The Allegro 17.2-2016 release enables several new capabilities for flex and rigid-flex designs to minimize iterations with MCAD and lower the overall cost for flex and rigid-flex designs. 

The stack-up by zones feature provides faster and easier definition of stack-ups for rigid-flex-rigid designs and improves MCAD-ECAD co-design. This new capability also enables material inlays for PCBs that have a small percentage of high-speed or RF circuitry on it. Material inlays can save up to 25% on boards with small RF/high-speed circuitry on them.

Another area of improvement includes extensive in-design rules for flex designs. This release introduces 12 new layers and 19 new finishes for flex and rigid-flex designs. More importantly, users can add new user-defined layers and surface finishes. The new in-design inter-layer checks provide the ability to check geometries between two different layers.  

2. New concurrent team design capability – work together simultaneously with your team members

Have a tight design schedule? Are you working with a distributed team on the same PCB design project at the same time? With the new concurrent team design capability in the Allegro 17.2-2016 release, you can work concurrently on the same design. By connecting users to a common Allegro PCB database, multiple designers can easily work on the design at the same time, and any changes made by one team member are seen in realtime by all members. The new Allegro concurrent team design feature can shorten routing time by up to 80% for dense and complex designs.

 3. New padstack editor – easy to use and supports many new pad primitives

The new padstack editor will dramatically increase your productivity when creating padstack through a modern, easy-to-use GUI. A wizard-like approach makes it easy to specify all attributes needed to define and specify a padstack. The new editor provides many new primitive padstack geometries to make it easy to create complex pad / padstacks. With this release users can create padstacks with several new primitive shapes like donut shape, rounded rectangle, or chamfered rectangle, to name a few. These padstacks are not only easy to create but also help streamline the rest of the design process. The 17.2 padstack also provides support for route keepout geometry as part of its definition -  objects can be controlled on each layer of the pad structure or on adjacent layers that can extend beyond the begin/end layers. Stay tuned for more.

4. The best backdrill capability in the industry just got better – easily navigate around vias marked for backdrilling

Allegro PCB Designer was the first to support backdrill capability many years ago. Based on customer feedback, we have enhanced the in-design rules for vias marked for backdrilling to make the design process even more efficient. In addition, we are providing better visuals around the vias marked for backdrilling to avoid creating problems / issues in the first place.

5. New cross-section editor - streamlines setting up of design, rules for stackup-related objects

The new cross-section editor provides set up for all the features such as stack-up by zone, dynamic unused pad suppression, and embedded component design. A dynamic graphical image of the stack-up construct is shown in a dockable window as you define the stack-up characteristics. The stack-up image includes functionality to set and show reverse drill direction. Grid-editing enhancements allow you to add layer pairs or a user-defined number of layers. Miscellaneous enhancements include the increase of material character length from 19 to 250, positive/negative tolerance support for each layer, via label customization, controls to prevent editing of layers or values, and support of unnamed dielectric layers above top/below bottom. Much more to follow in a future blog post.

6. Arc aware routing  with advanced contour hug saves time to route on flex designs 

Whether you are doing flex, rigid-flex or rigid PCBs, Allegro PCB Editor’s routing has been enhanced to be arc aware. The enhanced contour hug trace addition saves users time by providing a more efficient method to add routing during Add Connect by following an existing connect line or a route keepin. It introduces a simple canvas-based two-state click use model that also enables shoving of existing connect lines. Transitions between the non-contoured and the contoured routing are smoothed for line or arc corners. You have to try this yourself to see how easy it is.

7. Tabbedrouting - manage impedance and cross talk in critical signals, especially in BGA break-out regions 

Larger pin count devices and shrinking pin pitches are forcing narrower than usual trace widths. This, in turn, means that single-ended and differential pair signals have to meander through the pin fields, sometimes with arcs. To make matters worse, pin fields are full of voids on reference planes, making impedance uncontrollable. By migrating to Allegro 17.2-2016, you can have access to new ways to manage impedance on signals in such areas. You can control impedance by adding trapezoidal shapes on parallel traces, provide tab count and pitch validation, and manage and delete tabs when traces are edited. 

8. Allegro Sigrity, Better Together - Use “Sigrity verified” custom return path via structures in Allegro PCB Editor

Allegro 16.6-2015 introduced six new return path via structures that you can add. With the Allegro 17.2-2016 release, you can incorporate customer pre-verified via structures to save time laying out the design and avoid any surprises during the post-layout verification process.

9.  Ease-of-use Improvements

Making Allegro PCB Editor easy to use is an ongoing area of focus for us. In the Allegro 17.2-2016 release, we enhanced several features to reduce your time designing PCBs, to reduce your mouse clicks, and improve your customization capability. Now you can add customized commands to tool bars, and the Visibility Pane now allows designers to control layer content more quickly and more efficiently. There are several improvements in Allegro Constraint Manager, too.

10. New design rule checks

As with previous releases, we continue to enhance in-design rules in Allegro PCB Editor. In addition to new rules for backdrilling and inter-layer checks for flex and rigid-flex designs, we added new drill DRCs as well as four acute angle detection rules. For drill DRCs, you may recall that a few releases ago, Allegro PCB Editor enabled dynamic pad suppression, and at that time we introduced a new DRC “hole to other objects.” This DRC associated with dynamic pad suppression was only enabled when a pad is marked for suppression. With this release, Allegro PCB Editor allows you to enable drill-based DRCs on holes that have pads on them –  you can set and check for DRCs for padstacks whose pads are not marked for suppression. For angle-based rules we added these four new rules - minimum shape edge to edge; minimum line to pad angle; minimum line to shape angle; and minimum line to line angle.

To help you learn more about these new capabilities in the Allegro 17.2-2016 release and how you can benefit from them, we are launching this blog post series, 10 Top Reasons to Move Up to Allegro 17.2-2016 Release. Each week after this blog is published, we will delve into more details about each of the Top 10 reasons. Feel free to contact us if you have any questions, or would like to schedule a live demo with our technical experts. 

Hemant Shah

Adventures in Backdrilling

For the past 15 years or so, routing high-speed interfaces handling 5Gbps or higher have become more common in many electrical designs.   Transitioning high-frequency signals between layers can greatly affect signal integrity when a portion of plated through-hole (PTH) is left unused, forming an electrical stub.  In general, these stubs are a source of impedance discontinuities and signal reflections, which become more critical as data rates increase.

What options do I have to eliminate the electrical stub?

• Use a board fabrication process called backdrilling, sometimes referred to as controlled depth counter-boring.
• Carefully plan/restrict the high-speed interface routing to certain layers to minimize the stub effects. 
• Use Blind, Buried and Micro vias technologies for routing high-speed signals which has its share of limitations, concerns and added fabrication costs while not addressing press fit connector pins which commonly require backdrilling to eliminate the electrical stub.

In the early years, the fabrication vendor would identify backdrill opportunities based on critical net list and make all the appropriate adjustments.

Introducing a backdrill process to a design can sometimes be a nightmare to manage and requires working very closely with your fabrication vendor. The fabrication vendor will remove as much stub as possible on the identified high-speed signals, adjusting features at each backdrill location and verifying copper clearances due to the increased backdrill size to maintain design integrity.

To ease a transition to a more streamlined process, a stable foundation was developed in Allegro 15.7 to reduce the post processing of data at the fabrication vendor.

As a previous customer, I was part of the Allegro® PCB Designer 15.7 Beta Test Team in late 2005.  I was very excited to see/test the new Backdrill solution inside of Allegro.  The functionality pushed Allegro to a higher level by allowing designers to identify nets that require Backdrilling and apply several component and pin properties to influence the design analysis to identify backdrill locations.  Locations were identified in the Backdrill report, marked by special backdrill figures/legends for documentation and accompanied with manufacturing NCDrill files of backdrill locations for each specific depth.  Even with these enhancement there was still a number of manual steps to ensure the design integrity is maintained (supporting multiple padstacks for backdrill locations, manual backdrill keepouts and backdrill size adjustments at the fabricator)

As time went on, it was clear that further enhancements would improve the process by providing functionality to not only analyze design but also adjust features at the backdrill locations along with generation of a complete manufacturing data package to streamline the fabrication process.

Cadence worked with fabricators and customers to fine tune the existing solution to not only remove most of the post-processing steps by the fabricator but also enhance several areas of the tool in support of the backdrill process.  As a member of Product Engineering, I was able to influence the functionality based on my own past customer experiences as well as gathering feedback from our customers.

• Padstack supports the definition of backdrill data at the library.
  • Backdrill size with unique drill figures
  • Backdrill entry pad and Solder mask enhancements
  • Layer keepouts / clearance additions

Typical Backdrill Location

• Manufacturing stub length – remaining stub length after backdrill (advanced configuration)
  • Remaining manufacturing stub length measured down from the Must Not Cut Layer, which acts as a target backdrill depth into the dielectric

• Parameter based design level padstack updates built into Backdrill analysis.

• Improved model to quickly define / review backdrill layer pairs based on design analysis
  • Initialization: Deepest backdrill layer from top and bottom layers
  • Analysis: Minimized electrical stub length or minimize layer pair

• Backdrill diameter displayed with special drill labels to identify backdrill side/depth.
• Route keepouts automatically generated based on clearance defined in padstack
  • No more creating special padstacks or keepouts at backdrill sites.

• Show Element reports all backdrill data attached to pins/vias at backdrill locations
• Actual backdrill size is now reported in drill legends and manufacturing NCDrill files based on backdrill data defined in padstack
  • No longer necessary for fabrication vendor to adjust sizes based on plated through-hole
• Backdrill Legends now reports the Must Not Cut Layer, depth and manufacturing stub information
• Fabrication drawing cross-section detail now reports backdrill spans
• Full Test Point awareness during backdrilling process
  • No drilling away a test point or adding test points at backdrill sites.

This new enhanced backdrill solution takes all of the guess work and stress associated with introducing Backdrilling in a design.  No more increased Non-Recurring Engineering (NRE) charges at the fabricator, no more escalating costs associated with introducing different via and build-up technologies. Lastly a more complete manufacturing data package with backdrill data information contained in IPC-D-356 and IPC-2581 along with full documentation communicating backdrill intent to the fabricator.

Related Videos

Backdrill Demo Reel

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10 Top Reasons to Move Up to Allegro 17.2-2016 Release
What’s New in Cadence® Allegro® 17.2-2016 Release

We are not talking about how your design compares to the next guys’, we’re talking about the PCB layer structure of your design, be it rigid, flex, rigid-flex, or using inlay technology. Stackup definition, more specifically accurate stackup definition, is critical for a wide variety of reasons. The arrangement of the various materials affect the computations and analysis for controlled impedance nets and cross talk reduction which drives functional performance. ECAD/MCAD collaboration that expresses true substrate thickness, including mask layers is critical in modeling the physical aspects of a system, especially for those smallest or thinnest of devices that require the most efficient use of space. Most importantly, an accurate stackup definition is sent to the board fabrication facility for producing a final product that performs as the design data intended.

Material Inlay 

Rigid-Flex

Cadence^® Allegro^® PCB Designer 17.2-2016 makes it simple to define an accurate stackup structure for each of the design types previously mentioned. Our new Allegro PCB Editor Cross Section Editor provides the ability to define the dielectric and conductor layers, as well as external mask layers for rigid and flex designs. The Cross Section Editor enables you to easily define stackups for those single designs that must incorporate different stackups which use a variety of both conductor and non-conductor layers for flex, rigid-flex and/or inlay structures. Assignment of material is augmented through the use of a mask site definition file connected to the Cross Section Editor. The Mask Site file is managed by the user who creates a library of materials and standard mask layer names that are preferred by their company. When defining a layer in the stack, the user selects the appropriate layer name, and the layer and material are added into the stackup structure.

Mask Site File

Adding mask layers to the stackup is a simple process when building the stackup definition. When adding layers, the Mask Site File is read, and the layer names, and materials are presented to the user. When selecting the layer type, the assigned IPC-2581 Layer Function and material are highlighted for the user to see, but if one of the attributes requires a change for the particular design, simply selecting the new attribute from one of the lists updates the current assignment.

Create Layer Form

The Mask Site File is managed through the Site File Editor. This tool manages the IPC-2581 Layer Function type, Subclass name, Class and material for each stackup layer type that may be used in a design. Maintaining this data provides consistency between designs and reduces typo’s that may occur. Once created, the Mask Site File is stored into the MATERIALPATH location where all users have access to this file.

Mask Layer Site File Editor

Easily Define Multiple Stackups in Cross Section Editor

Defining multiple stackups in the Cross Section Editor begins with enabling the Multi Stackups Mode (View->Multi Stackup mode). The user then defines the entire cross section paying careful attention to the order of layers and materials used for the design. The Primary column identifies the default stackup structure for the design. Selecting the check box in the Primary column adjacent to the layer identifies the layer as part of the Primary stackup. To create another stackup, just select Add Stackup column (or EditàAdd Stackup, or select the tab labeled “+”), enter the new stackup name in the Create Stackup form and the new stackup is added into the mix. Assign the layers for the stackup by checking the boxes and you’re done. The Cross Section Editor also updates the graphics to the right of the stackup tables for a quick visual reference. The user can export the finished cross section definition to a Cross Section Technology file making the identical structure available for other designs.

Multiple Stackup Definitions

Remember that remark about accurate documentation? Once the stackup structure is defined in the Cross Section Editor, one of the benefits is the ability to create a stackup table for documentation. The same data defined in the Editor can be extracted to a table in the fabrication drawing which the fabricator uses in their process. The fabricator now has the information on materials and structure to build your design accurately.

Stackup Table Example.

With the new Allegro 17.2-2016 release, the enhancements to the Cross Section Editor have provided a complete approach to defining an accurate stackup definition with mask layers, consistent layer names, and documentation details. Now you ask, “Nice, but how can I use these new features in my actual design?” Look forward to the next session “Zoning In on your Design with Allegro 17.2-2016” where more will be uncovered in using Multi Stackup capabilities.

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10 Top Reasons to Move Up to Allegro 17.2-2016 Release
What’s New in Cadence® Allegro® 17.2-2016 Release

Enhanced Contour Routing is a new prototype feature in the Cadence® Allegro® PCB Designer 17.2-2016 that provides a more efficient method to add routing during Add Connect by following an existing connect line or a route keepin. This feature has been vastly improved over the legacy Contour feature by removing a continuous dialog popup, introducing a simple canvas-based two-state click use model, and enabling Shove of existing connect lines, even with Arc corners. Transitions between the non-contoured and the contoured routing are smoothed for line or arc corners.

Enabling Enhanced Contour

Once Enhanced Contour is enabled in Route > Unsupported Prototypes > Enable Enhanced Contour, the Enhanced Contour Right Mouse Button selection becomes available during interactive routing.

Two State Click Use Model

Once Enhanced Contour is activated during Add Connect, there will be a behavioral and graphical change on the canvas. When you are within proximity of a connect line or keepin, the prospective contour template will highlight and the active connect line being routed will be prevented from shoving or going closer than the desired gap (min DRC spacing plus any Extra Gap specified).

If you click while the connect line or route keepin is highlighted, you will be locked into the contour state – route will be contouring to highlighted object. If you click again, the route will then move freely away from the contour template. You can switch modes in and out of "contour enabled" at any time.

As always your comments are welcome!

How have you used rigid-flex in your designs?  What are your top three tips to share? Please sign-in above and start contributing to the community discussion.

Related Videos

Allegro PCB Rigid Flex Demo Reel

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10 Top Reasons to Move Up to Allegro 17.2-2016 Release

Cadence Allegro Rigid-Flex Overview on Cadence.com

Improve Route Channel Utilization with Tabbed Routing

Tabbed routing is a new method in which trapezoidal shapes called tabs are added to parallel traces to control impedance in the pin field/breakout regions, and reduce crosstalk in open field regions. It is a breakthrough routing strategy that allows for longer trace lengths and more compressed routing.

Unfortunately, this new routing technology increases layout complexity and managing these tabs later in the design process can be a nightmare.

PCB layout designers rejoice! We have heard your woes and pleas for help.

Aside from providing the means to generate the trapezoidal tabs, we have covered the entire tab "life cycle" with several unique features. 

Generate Tabs

First stop is tab creation. Select mode, enter tab size/pitch values under parameters, and select parallel cline segments to generate tabs. You can also load your saved parameters to quickly generate tabs on different areas and/or interfaces.

Analyze Tabs

Perhaps the special feature we are most excited about is the capability to Analyze Tabs. It provides an integrated and more efficient way for users to validate tab count matching and pitch. Create custom rules for pass/fail criteria and cross probe violations in canvas for fast fixing. Generate custom tab count and pitch reports to suit various data needs.

Manipulate Tabs

We offer several unique features to help handle these tabs easily. Tab in the wrong location? Easy fix with Move Tab which provides ability to move a tab along segment while maintaining centerline connectivity. It also provides dynamic DRC feedback so you can easily resolve those spacing violations. Need to quickly remove some or all of the tabs? Our Delete Tab provides a fast and easy way to delete tabs by clines, cline segments, or tab instance.

Our interactive etch editing features are also now tab aware – so tabs are intelligently copied or removed along with the segments. Tabs are no longer left floating in the design when you delete or slide segments. And it is now easier than ever to copy routes with tabs and replicate to other byte groups - copy multiple clines/segments with tabs and snap to pads or cline segments.

You won’t find a more comprehensive tool for the job.   What are you waiting for?

High Speed Routing Demo Reel

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Back to “10 Top Reasons to Move Up to Allegro 17.2-2016 Release”

Related material on "What’s New in Allegro" on Cadence.com

Go deep with tabbed routing with this link to whitepaper.