By John Burkhert Jr

I want to take you back to a project that highlights a few twists as all good projects will. 17 years ago I was presented with 20 pounds of potatoes and a 10 pound bag. The bag was shaped like a PEZ dispenser with a crown of gold fingers in place of the plastic head. The actual name of the early form factor was XENPAK. It used the XAUI protocol which has become a  popular 10G-for-the-masses deal. My piece of the puzzle sat between the fiber optic backbone and the edge routers that supplied data to medium and large enterprises.

That inside-out effort lead to an “It’s not you, it’s us” story about how they didn’t need anything from us for a while.

As an aside, Cisco accounted for about 80% of the merchant market for these transponders. The “merchant market” is the part where the industry is not doing that layer in-house. A small company filing a socket for a huge company is a pretty common scenario. The big guy  sneezes, and you get pneumonia for roughly 13 weeks. They liked our stuff and ordered a lot. Then we delivered, possibly beyond their expectations. That inside-out effort lead to an “It’s not you, it’s us” story about how they didn’t need anything from us for a while. Food for thought on how the big manipulate the small. They did award us a technology alignment award for our flagship product – just before canceling our quarter on the 10G part – so we had that going for us, which was nice; sort of.

Photo Credit: Opticore - Typical XAUI based 10G device

The Thick (or Thin) of the Plot

Back in that simpler world based in the weeks before 9/11, a good laser and photodetector were some chunky components. The special goodness we were adding was a device that reduced chromatic dispersion, whatever that is, and it allowed us to double the distance between repeater stations along the fiber network. This component was my first exposure to 0.5 mm pitch devices. This pitch, if you didn’t already know, is the threshold where micro-vias become a thing. Mid 2001 was still early-adopter times for HDI, so I definitely had the fab-shop on speed-dial.

These high-performance parts can blink a laser on and off 10,000,000,000 times in a second while reading the blinks from another laser at the same bit rate. When you ask this much of your equipment, it will inevitably end up with an exothermic reaction; toasty IT closets for everyone! We had to check that problem with active cooling. We put a Thermo Electric Cooler (TEC) right between the transmit and receive chains. You will find these TEC devices in the portable coolers that plug into those strange, round, 12V power ports they put in cars. Ok, most of us know them as cigarette lighters. The point is that the “friggin’ laser” and the detector, along with their insatiable appetite for LC filtering, had us over-committed on component placement by about 50%. Call it 7.5 pounds of potatoes and we have to stop short of mashing them together in the PEZ dispenser.

The Squeeze Is On

Connectors were also going through the fine-pitch revolution. We found a stacking connector that gave us a one-millimeter clearance between the top of the lower board and the bottom of the upper board. Not exactly the kind of space PCB dreams are made of. The connector itself needed about ⅓ of the board space on one side of the mother as well as the daughter. If the space of one board is equal to one, the net space after the connectors across two boards comes out to around one and a half.

Feasible, in theory, if you can make good use of the one millimeter between the two boards. It was at this time that I began putting the component height on the layer that defines each footprint’s X and Y extents. This is useful information to have whenever the board’s overhead space is at a premium. A one-millimeter tall inductor would result in zero head-room in that corresponding area on the other board. It wasn’t as though either side could have half of the headroom and pull this off. The contours of one define the limits of the other.

Splitting the Schematic

Breaking up the circuit came down to one characteristic: the 10G path had to come and go on the bottom board. There was no RF, no micro-vias, and no selective gold finish on a regular four-layer FR4 daughtercard. I still recall that the vendor had no DFM issues on the cheap board. My manager at the time had no tolerance for feedback from the fabricator. He read those calls and e-mails as documentation or engineering failures. We typically read them as standard line width and material negotiations. You can thank that nameless but brilliant man for all those times I’ve told you to get your stack-up approved ahead of the routing gate.

Moving Right Along

The newly minted daughter card was only smaller than its parent by the mom’s gold fingers. Removing everything we possibly could and squeezing through an interactive placement of shared headroom was just enough to pull it all together. It was a small company called Big Bear Networks, and I had one PCB Layout contractor on board with me. The layouts would be super dense because we would use the same core circuit for the XENPAK DWDM and a couple other transceiver form-factors. Overlap the three outlines, and only the common area is for component placement. In this way, we could deploy different SKUs using the same basic circuit.

Given such tight confines, I challenged the contractor, and we both tried to complete the placement within the common area. I was still trying to place the last two parts when he completed his version. Nearly all of his shunt elements were facing the edge of the shield with the ground pin out. It lengthened the inductive loops a bit but gave that extra sliver of room. His version also sent a segment of the 10G TX line to an inner layer. Mine was an outer layer solution with all of the shunted elements rotated with their ground pins towards the transmission line. I wanted everything with no compromise. Anyway, full stop. The consultant completed his lower board while I generated the upper board using an imported image of his placement for reference.

Image credit: Finisar - X2 form factor, one of the smaller Multi-Source-Agreement platforms for XAUI.

Winner, Winner, Chicken Dinner!

The boards came in, everything fit and the thermal readings were under control. The engineering samples had beautiful open eye diagrams, and the big Cisco order followed. You know the rest except the part where I eventually left this operation to flip the bit back to analog and rejoin previous management at a new company with a wider customer base. Then, as now, the valley (and the world) thrives on new ideas. Keep up your skills and keep getting those design wins.

By John Burkhert Jr

Bringing a multiboard system together is a chance for the designer to spread their wings. As the circuit spreads, so do the risk of crossed signals. Some of the ways the circuits can get scrambled include:

• Some connector vendors have clear indications of polarity. Others leave all numbering to the buyer. In the same way, a row of gold fingers will be anything we draw up in terms of pin numbers and signal names.
• While the physical design typically depicts the orientation of a connector by indicating the location of pin one, rarely is the net that goes on the circuit defined at that level.
• Each board in the system has a separate schematic, probably drawn up by a subject matter expert that naturally varies from one board to another.
• A connector can be mirrored to the secondary side, yet we can view it as though we had Superman X-ray vision.
• A single large connector can have a cable or flexible circuit that mates to it but then splits the larger connector’s signals into several smaller connectors that get distributed all over the system. Each of those branches will have a pin-one of its own but only one of them at the end where everything is collected together.
• Rogue changes on one card can derail a system.
• Library inconsistencies and simple mistakes can as well.
  

Closing all of those potential open loops takes a degree of organization. The system level physical designer is very concerned with everything fitting together. PCB Designers are working within their outline(s) and can also become a bit myopic in that regard. It seems as though we go over these things ad nauseam in the early design reviews when the high-level architecture is being laid out. Then, some bug crops up when we put everything together. What happens? How can we stay on an even keel?

Block it All Out

I don’t mean therapy or hitting your head against the wall. Block Diagrams, Wiring Diagrams, Interconnect Diagrams, Interface Control Diagrams, Outline Drawings, and beautiful 3D renderings all help put the big picture in perspective. They may also be considered too mundane for the critical path and be put off until everything is completely defined. What happens then is that any disconnects get cleaned up in the pre-production run. New boards/cables/flexes are rushed out and all of the expediting and long days go into trying to mitigate the risks before going to mass production. Turning up volume production on something that is mostly tested and verified is one way to live on the edge. So is blindfolded paragliding. Nobody talks about the time their parachute didn’t open. Fewer mistakes in the prototype stage pay the dividend known as peace of mind as we confidently scale up our efforts.

The bigger the job, the more we need to employ risk management in the form of stronger documentation. Nobody does testing and documentation quite like NASA, but the auto industry is really good at supply chain management. When you become part of the supply chain, you quickly become well managed. You get to generate all sorts of documents related to design verification at all levels. Just as you are managed, you become a technical manager to your suppliers as they do for theirs. But I digress.

Creating Order From Chaos, One Step at a Time

The thing is that this level of scrutiny is not as common in the typical consumer hardware setting. Getting your engineering folks to draw up a proper interconnect table may be a stretch. Starting your own “quick and dirty” version is better than nothing and may even prompt the team to fulfill their ideal destiny. We’re after a schematic of schematics. There is a lot of abstraction at this level. A box represents a board, and a list in the box represents the functional connectivity between the various boards.

Image credit: Research Gate - Use more or less detail as required

A system power tree is another important reference point. The number of functions a product has will be a close indicator of the different number of power domains required. Let’s say, for instance, that we have a camera and a display to go with a microphone and speakers to make an Arduino conference room package. All five of those items will want their own power supply even when they are designed for the same number of volts. Scale up to the devices with over 1000 pins and each little area of the device wants a particular power source all its own. They give me an 800-page owner’s manual for the Intel Skylake device. You’d shake your head at that ball-map. It does have an excellent power tree along with the reference design material though.

Life on the Analog Frontier

We got the chance to create a reference design for a Samsung Chromebook Plus. We had the main logic board and a handful of outlying boards. GPS, for instance, needed a quiet area so it could receive the small signals from the satellites. I mean quiet in an electromagnetic sense. The speakers still qualify as a problem because of their magnets. The metal enclosure, the WIFI, the Bluetooth and a number of sensors were all problems.

Coexistence is the name of the game when we try to make all of these disparate functions work together. Simulations will take us a long way, but there are blind spots. You don’t know until you have everything packed into the form factor and turn it all on. Who can forget the time that people wrapped their hands around the upper area of the new iPhone and were told that they were “holding it wrong”? The Pixel phone with its band of non-metal color is an indication of where the invisible connections are taking place through various antennas.

The short answer is that wireless connectivity is the risk that is hardest to manage. For the most part, we try to contain electromagnetic waves. In this case, we’re making them on purpose. The more wireless protocols you have, the more corner cases to explore. Life is better if you only have to tame one radio. Your phone is a war zone of conflicting interests. This laptop was no different. The prototypes were not 100% ready for prime time. The project was pulled together with a few schematic revisions including more filters and regulators; small stuff for the P1 stage except for mis-wiring the battery connector! Mass production followed on with minimal drama. I can say that now, but I was 10,000 miles from where most of the action took place. I know they worked hard too.

Image credit: Author - You’d think we could do something as simple as a battery connector.

The result was thin, light, fast, robust and flexible enough to wrap itself into a tablet, stylus included. Here is a glowing video review of the hardware. Spoiler: the man spent 12 minutes talking about this one laptop and did not have any negatives. Could it be that good? The awards at CES ‘17 were long and strong. This is the ARM processor version that has a lookalike big brother with the Intel SOC. The reviews tend to reflect that this is the lower tier of the Samsung premium convertibles. Working with the outside vendors on the reference designs was interesting.

They provided very detailed .dxf files so we could import geometry directly to the layout. The inner workings of the laptop were rendered over several layers. In a way, that was even better than drawings. The ODM (original design manufacturer) also had the wherewithal to take on the system interconnect review. Between the software models and mock-up hardware, the away team executed a nice product on a three-spin development cycle. Prototypes are the breadboard version without any physical limitations. Pre-production is the first time all of the components are joined in the form factor, and the third cycle is the one that you can still buy. Or not. I have pride in the work but, Samsung doesn’t share anything with me. They are in-house for their designs anyway. We provided a six-layer option to their eight.

Image credit: Author - The P1 version of a motherboard for a laptop/tablet chromebook

Great systems start with solid documentation, strong communication, and trust that everyone is going to hit their mark. The first iteration is to see if things work. The second is to see if it fits and the third has to have 100% of both of those things. In the words of the cold warriors of ancient times, “Trust but verify.” Multiboard systems are expected to be complicated by their nature. The different voltages have to be over- and under-powered in different combinations and over varying temperatures and so on. With all that is expected of these costly systems, it is incumbent upon the designer to take care that the system level connections are fully vetted before the die is cast.

Interested in an easy-to-use, collaborative, and robust design-environment that reduces design cycle? Use, Cadence® Allegro® and OrCAD® release 17.2-2016.  Here are the 10 Top Reasons to Move Up to Allegro 17.2-2016 Release This enables you to accelerate your PCB design cycle. 

Get started immediately with the new release using the central page on https://support.cadence.com. It lists important links to Allegro and OrCAD 17.2-2016 documents. Visit the “one-stop shop" page to get all you need to install and use the release.

Visit the page - https://support.cadence.com/SPB172launch

These pages list What’s New, videos, application notes, migration guide, and other online help documents. In the left pane, select Getting Started for release-level information or select a product (for example, Allegro PCB Editor) for information about it.

Allegro PCB Editor

Allegro Design Entry HDL

Allegro Design Entry CIS (OrCAD Capture)

Allegro AMS Simulator (PSpice)

Visit the page - https://support.cadence.com/SPB172launch for more.

Contact us for any questions. Leave a comment in this blog post or use the Feedback / Like mechanism within https://support.cadence.com.

Happy New Learning!

~Jasmine

Cadence Online Support has this Rapid Adoption Kit (RAK) on Rigid-Flex in Allegro PCB Editor 17.2 that introduces a flow to define unique stackups by physical zone. The Cross Section Editor in 17.2 has been enhanced to support multiple stackup definitions including support for mask and coating layers. The primary driver for this enhancement is Rigid- Flex applications where it’s common to have different fabrics across the final PCB product. Benefits will also be realized for customers designing standard Rigid PCBs. Soldermask and Solderpaste and their thicknesses can be added above/below the surface layers. Rigid PCBs may also require inlay material zones for RF/Analog circuits.

This RAK covers …

• Adding Non-Conductor Layers to Cross Section

• Multiple Stackup Entry

• IPC2581 Layer Functions

• Adding/Editing Physical Zones in the PCB Editor

Rigid-flex technology lets us create smaller PCBs than ever before. Watch the video on Serious tools for advanced rigid-flex

Cross Section Support of Non-Conductor Layers

The PCB Editor Database represents non-conductor layers as “Mask” or “Dielectric” although they may serve different purposes like coating or plating areas. To add a mask layer above layer Top, select the Top cell in the Cross Section grid then use the RMB to access the “Add Layers” command as shown in the graphic below.

The new Surface Finishes Class supports the following subclasses …

Multi-Cross Section Support

The Cross Section Editor has been enhanced to support multiple stackups, each capable of supporting conductor and non- conductor layers such as Soldermask and Coverlay. The Cross Section Editor provides total thicknesses for each stackup in terms of accumulated conductor layers as well as a mask layer option.

Multi-Stackup Grid

Layer Functions (IPC2581)

The Cross Section Editor now supports IPC2581 defined Layer Functions. These user selected Layer functions are defined as attributes in the IPC-2581 stack-up layer definition for fabrication instructions at the manufacturing level. Customers utilizing the 2581 standard for data transfer may want to consider these options. The diagram below reveals the full set of layer function options.

Dielectric layer types support the following options …

Physical Zones

Zones are physical areas in the design that map to one of the available stackups in the cross section editor. Zones are added using the standard add shape or add rectangle commands found in the Setup – Zones menu. Mapping a stackup to a Zone may occur at the creation of the Zone, or assigned through the Zone Manager after the Zone is created. Constraint Regions and Rooms may also be assigned to Zones at creation or through the Zone Manager.

When adding a Zone, you can loosely define the boundary during the creation command as it will snap to the design outline geometry upon completing the command. In the left figure below, a zone boundary is extended beyond the actual design outline. It eventually snaps to the actual design outline when the add shape command is completed.

Inter Layer Design Rule Checks

This RAK also explores Inter Layer checks that provide a new tier of checking of mask to mask and mask to other geometry types providing the user with problem detection earlier in the design to manufacturing cycle.

             In typical rigid-flex designs, various stackup definitions are assigned into different zones where the top or bottom level might differ zone to zone. In traditional workarounds, the package symbols require special attention to padstack definitions, special “flex” symbols, and so on, or use the embedded component process to place these symbols onto the correct layer for not only artwork purposes but for documentation as well. You may refer the document on Dynamic Zone Placement in Allegro PCB Editor 17.2  here. This reviews the PCB Editor's awareness of varying top surface layers in a multi-zone rigid-flex design during placement.

Click here for the Rapid Adoption Kit and for the detailed step-by-step procedures on the Rigid-Flex functionality, as well as various other aspects that are not covered in this blog.

Note: The above link can only be accessed by Cadence customers who have valid login ID for https://support.cadence.com

Related Links

Learning Advanced Flex and Rigid-Flex Design Support in Allegro 17.2-2016

Why Move Up to Allegro 17.2-2016? Advanced Flex and Rigid-Flex Design Support (Reason 1 of 10)

Cadence Allegro Rigid-Flex Overview on Cadence.com

Ensuring Reliable Products with New Rigid-Flex Design Rules

Finding a way out of situations is routine in today’s ever changing world—more so in the world of tech. Our problems range from trivial to critical. Mostly, people look for simple solutions that are easy to use. How sometimes a quick note can resolve a nagging problem! And a smart solution with a video simulating steps helps resolve issues even more quickly and satisfactorily. 

This is exactly what we are now doing at Content Support Portal.  We have articles with videos showing relevant steps.

You never miss out any step while you are trying it in your designs.

Here is how it looks like:

Visit Content Support Portal for more such video-embedded articles on major products. For example, if you want to set up differential pairs in Constraint Manager so they are spaced 20 mils from other nets,  click here.

Some more examples of enhanced features elaborated in short videos within articles:

Allegro PCB Editor

• What are the improvements made to the docking panes in Allegro PCB Editor version 17.2?

• How to customize toolbars in Allegro PCB Editor version 17.2?

• Sliding cline segments or vias using the "IX" and "IY" incremental commands

• Rotate groups of components and preserve their relationship to each other

Allegro Design Entry CIS (OrCAD Capture)

• How to protect an Allegro Design Entry CIS (Capture CIS) design with a password

• How can I force Capture to read custom configuration files (like allegro.cfg or Prefprop.txt)?

• How to select a different license from within Capture and uncheck the default license

Allegro AMS Simulator (PSpice)

• How to create the model for a Zener Diode

• How can I run advanced analysis from my normal PSpice design?

We hope you find it useful and look forward to your feedback.

Leave a comment in this blogpost or use the Feedback / Like mechanism within Content Support Portal.

~Jasmine

Recently, CDNLive China was held in Shanghai. What are the highlights of PCB Track? What are the latest news in the industry? What are the development strategies for Cadence PCB/Packaging? We conducted an exclusive interview with Mr. Saugat Sen, Cadence Allegro R&D Vice President

Figure 1 Mr. Saugat presented Outstanding Paper Award to Spreadtrum

Figure 2: CDNLive China

Figure 3 In PCB Track. Saugat delivered a keynote speech named Enabling System-Level Design with Allegro Technologies.

Interview with Mr Saugat

After the conference, we had the privilege of an exclusive interview with Mr. Saugat. Here are your questions answered:

1, What's the development strategy of Allegro for the future hardware design?

Allegro has been evolving to address the larger issues of system design, aligned with Cadence’s strategy of System Design Enablement. We recognize that the customers’ design challenges today are inter-disciplinary. There is a need to blend implementation and analysis, there is a need to identify manufacturing issues early in design, there is also the need to enable collaboration across mechanical and electrical domains. Our strategy is to collaborate with leading customers across the world, to innovate and leverage all our technology assets to enable solving design challenges that span Chip, Package, Board and the system of multiple boards.

2. How to shorten time to market?

One of the key vectors that we are driving Allegro on is to significantly improve customer productivity. Our concurrent team design solution - Allegro PCB Symphony Team Design solution is just one example of enabling this. We are making ECAD/MCAD co-design seamless, and blending analysis and design closely. It is our endeavor to evolve Allegro to make  transformational improvements in our customers’ ability to shorten the PCB design cycle time.

3, How to ensure the success of manufacturing in the future?

We have multiple solutions to address the needs of design for manufacturing success, including new Cadence Allegro DesignTrue DFM Technology, the industry’s first solution to perform real-time, in-design design-for-manufacturing (DFM) checks integrated with electrical, physical and spacing design rule checks (DRCs). Our experience with customers leads us to believe that we need to identify the issues as early as possible in the design process so as to reduce the end to end PCB cycle time.

4, What do you think of China PCB/Packaging market?

China is clearly establishing its thought leadership in technology across multiple domains. While companies in China has been doing leading edge work in PCB for many years, we expect a similar trend in IC Packaging as well. We are fortunate to be in a position to collaborate with our customers in China. We look forward to partner with them in evolving our technology to serve their needs and our customers worldwide.

Team Allegro

Accelerating product time to market, achieving significantly higher productivity and efficiently working in global engineering teams are the key challenges being faced by designers. Team Design Authoring (TDA) feature of Allegro Design Entry HDL addresses these challenges by providing integrated team design environment. The design can be partitioned at a sheet or block level, and each designer can be assigned one or more blocks or sheets. Any number of designers can work on different parts of the same design simultaneously without interfering with each other. The various design stages can then be combined before proceeding to layout in Allegro PCB Editor. This concurrent design approach makes Allegro Design Authoring extremely productive for large designs. Designers work on the board layout and schematic in parallel.

Cadence Online Support has this Rapid Adoption Kit (RAK) on Team Design in Allegro Design Entry HDL 17.2. The RAK covers:

• Setting up team design environment
• Enabling team design
• Joining team design as member
• Working with designs in team design environment – doing check-in and check-out

Setting up team design environment

This is the first step of team design and involves accessing the user list, granting permission to users, defining Integrator roles, updating libraries and designs and setting up project shared area.

Enabling team design

After setting up team design environment, key task is to enable team design (ETD) for a project and is done by the integrator.

When you enable a project for team design, the following happens:

• Subdesigns are assigned to team members and can be used by designers by joining the project.
• The selected design project is now in the shared area.

Joining team design as member

After the integrator has set up the shared area and assigned ownership rights for sub-designs, designers access the project and start work on the sub-designs they own.

Working with designs in team design environment – doing check-in and check-out

The TDO user interface offers tooltips and icons to help you perform various data management tasks that include check-in/check-out and doing modifications.

Click here for the Rapid Adoption Kit and for the detailed step-by-step procedures on the Team Design functionality, as well as various other aspects that are not covered in this blog.

Also watch the video on Enabling a DEHDL project for Team Design.

Note: The above link can only be accessed by Cadence customers who have valid login ID for https://support.cadence.com

Recently, CDNLive China was held in Shanghai. What are the highlights of PCB Track? What are the latest news in the industry? What are the development strategies for Cadence PCB/Packaging? We conducted an exclusive interview with Mr. Saugat Sen, Cadence Allegro R&D Vice President

Figure 1 Mr. Saugat presented Outstanding Paper Award to Spreadtrum

Figure 2: CDNLive China

Figure 3 In PCB Track. Saugat delivered a keynote speech named Enabling System-Level Design with Allegro Technologies.

Interview with Mr Saugat

After the conference, we had the privilege of an exclusive interview with Mr. Saugat. Here are your questions answered:

1, What's the development strategy of Allegro for the future hardware design?

Allegro has been evolving to address the larger issues of system design, aligned with Cadence’s strategy of System Design Enablement. We recognize that the customers’ design challenges today are inter-disciplinary. There is a need to blend implementation and analysis, there is a need to identify manufacturing issues early in design, there is also the need to enable collaboration across mechanical and electrical domains. Our strategy is to collaborate with leading customers across the world, to innovate and leverage all our technology assets to enable solving design challenges that span Chip, Package, Board and the system of multiple boards.

2. How to shorten time to market?

One of the key vectors that we are driving Allegro on is to significantly improve customer productivity. Our concurrent team design solution - Allegro PCB Symphony Team Design solution is just one example of enabling this. We are making ECAD/MCAD co-design seamless, and blending analysis and design closely. It is our endeavor to evolve Allegro to make  transformational improvements in our customers’ ability to shorten the PCB design cycle time.

3, How to ensure the success of manufacturing in the future?

We have multiple solutions to address the needs of design for manufacturing success, including new Cadence Allegro DesignTrue DFM Technology, the industry’s first solution to perform real-time, in-design design-for-manufacturing (DFM) checks integrated with electrical, physical and spacing design rule checks (DRCs). Our experience with customers leads us to believe that we need to identify the issues as early as possible in the design process so as to reduce the end to end PCB cycle time.

4, What do you think of China PCB/Packaging market?

China is clearly establishing its thought leadership in technology across multiple domains. While companies in China has been doing leading edge work in PCB for many years, we expect a similar trend in IC Packaging as well. We are fortunate to be in a position to collaborate with our customers in China. We look forward to partner with them in evolving our technology to serve their needs and our customers worldwide.

Team Allegro

Accelerating product time to market, achieving significantly higher productivity and efficiently working in global engineering teams are the key challenges being faced by designers. Team Design Authoring (TDA) feature of Allegro Design Entry HDL addresses these challenges by providing integrated team design environment. The design can be partitioned at a sheet or block level, and each designer can be assigned one or more blocks or sheets. Any number of designers can work on different parts of the same design simultaneously without interfering with each other. The various design stages can then be combined before proceeding to layout in Allegro PCB Editor. This concurrent design approach makes Allegro Design Authoring extremely productive for large designs. Designers work on the board layout and schematic in parallel.

Cadence Online Support has this Rapid Adoption Kit (RAK) on Team Design in Allegro Design Entry HDL 17.2. The RAK covers:

• Setting up team design environment
• Enabling team design
• Joining team design as member
• Working with designs in team design environment – doing check-in and check-out

Setting up team design environment

This is the first step of team design and involves accessing the user list, granting permission to users, defining Integrator roles, updating libraries and designs and setting up project shared area.

Enabling team design

After setting up team design environment, key task is to enable team design (ETD) for a project and is done by the integrator.

When you enable a project for team design, the following happens:

• Subdesigns are assigned to team members and can be used by designers by joining the project.
• The selected design project is now in the shared area.

Joining team design as member

After the integrator has set up the shared area and assigned ownership rights for sub-designs, designers access the project and start work on the sub-designs they own.

Working with designs in team design environment – doing check-in and check-out

The TDO user interface offers tooltips and icons to help you perform various data management tasks that include check-in/check-out and doing modifications.

Click here for the Rapid Adoption Kit and for the detailed step-by-step procedures on the Team Design functionality, as well as various other aspects that are not covered in this blog.

Also watch the video on Enabling a DEHDL project for Team Design.

Note: The above link can only be accessed by Cadence customers who have valid login ID for https://support.cadence.com

Let me tell you a funny story.

We’ve been working with an outside research agency to write an eBook with new insights into ECAD data management. And based on the findings, I wanted to write a blog about how risky it is to just put your ECAD data on a network or shared drive with a file and folder structure. I thought I had a pretty solid first draft of that blog post written before going away for Christmas.

We were moving from one shared storage system to a new one. I always stored my files in a shared folder so everyone on the team could access and edit them, much like many groups manage their ECAD data today. Since I knew we were migrating systems during the holiday, I made a complete backup of my data locally and slept fine for two weeks while on vacation. 

And when I came back... Gone.

Even today, I still don't know where it went. 

Where Are Your Files, Dude?

Maybe it was the file names, perhaps my backup didn’t complete... I have no idea. But my blog article and my search ads for the eBook are gone. Trust me, the irony of losing a blog post about the risks of poorly managed data is not lost on me.

Oh well, I'll just rewrite the article and ads and have an ironic (I swear this is true, this actually happened and I'm actually redoing the work) story to tell. And believe me, I’ll be using a proper data management system instead of a network drive from now on.

A blog post, some ad copy, not really a big deal.

What if it was design data? What if it was your customer's design data? How long would it take to recreate it? How much shade would your coworkers throw your way if you deleted their data from a network drive and they had to spend the weekend recreating it? How embarrassing would it be to go back to the customer and say you lost their files and needed them again?  At best, you’re spending time on non-value add tasks in looking for and recreating missing data. At worst, you may have a customer data or security concern and you might be spending non-value add time looking for a new job.

I thought I had a pretty fool-proof folder structure and file naming convention setup. I even had a local backup. And I still lost my files. Want to know the scariest part: I don't even know what all is missing. So far, I know I've lost a blog post and some ad copy. But maybe there's more...

They're Right Here, Dude

So here we are, the week after I get back from Vacation. And I get an email from my boss. “I messed up” the subject line reads. He’d been editing a PPT on the network drive, deleted some slides he didn’t need, saved it (overwriting the original), and then realizing his mistake, proceeded to delete the whole PPT.

(Also a true story; I couldn’t make this up!)

No worries. Now that I have a data management system in place, I reverted back to the original and no one needs to know.

Download the Free eBook

Anyways, check out this eBook about ECAD data management. And please, be better about your design data than I am with my Word documents.

When it comes to choosing a design-capture tool in the EDA world, there is no one-size-fits-all solution. Depending on a variety of factors, most of all personal preferences, the answer to “Which is the best design-capture application?” keeps changing. Most design tasks can be accomplished in all tools. Some tools might even look similar.

In this scenario, what differentiates one product from the rest is highly subjective. Usability, or ease of use combined with efficiency, is a key determinant. A user might ask: 

• How much do I need to know in advance? How much do I need to figure out?
• How many clicks are needed for doing the same task?
• How well does it work with other applications in the design-to-fabrication flow?
• How easy is it to extract information for different departments?
• Does it include a robust library? Can I extend the available libraries?
• Can I reuse my designs?
• How much of it is automated?

Allegro System Design Authoring (SDA) is a powerful, enterprise-level application that addresses these concerns and brings you the robustness of Design Entry HDL and the lightness of OrCAD® Capture. SDA offers a gamut of new features and simpler, faster ways of completing design-capture tasks. Let’s take a look at the top 10 of the many features of Allegro SDA and how they benefit you, the designer:

This just begins to scratch the surface. SDA not only looks modern, it has built-in mechanisms that are contemporary and smart. Even though the interface and use models are intuitive, SDA Help includes a robust library of technical videos that quickly demonstrate SDA features and an FAQ that addresses the most common questions. When you work with SDA, your design efficiency improves, and you'll realize how the entire PCB design ecosystem gets connected and streamlined.  

The next generation of schematic entry is here.  

For more information about SDA visit:  http://support.cadence.com/wps/AllegroSDA

Using Sensitivity Analysis of PSpice

I was thinking of writing a series of blogs showcasing what all ammunition's a circuit designer may need to deal with any complex circuits today. So, here's the first one. 

When in college, books tell you everything about your circuit. You already know which components are critical in your designs. But, what about when you enter an industry? You have completely new designs that you build or come across and you need to know which components are critical for your measurement goals. The first thing a designer has to be sure of is to thoroughly understand/ know their circuit. 

In the first Tech-Blog of this series, we will take a sample RF Amplifier circuit and perform PSpice Sensitivity Analysis on it. Read more into how this Advanced Analysis capability helps you reduce circuit design costs considerably.

Continue Reading on PSpice.com

Accelerating product time to market, achieving significantly higher productivity and efficiently working in global engineering teams are the key challenges being faced by designers. Team Design Authoring (TDA) feature of Allegro Design Entry HDL addresses these challenges by providing integrated team design environment. The design can be partitioned at a sheet or block level, and each designer can be assigned one or more blocks or sheets. Any number of designers can work on different parts of the same design simultaneously without interfering with each other. The various design stages can then be combined before proceeding to layout in Allegro PCB Editor. This concurrent design approach makes Allegro Design Authoring extremely productive for large designs. Designers work on the board layout and schematic in parallel.

Cadence Online Support has this Rapid Adoption Kit (RAK) on Team Design in Allegro Design Entry HDL 17.2. The RAK covers:

• Setting up team design environment
• Enabling team design
• Joining team design as member
• Working with designs in team design environment – doing check-in and check-out

Setting up team design environment

This is the first step of team design and involves accessing the user list, granting permission to users, defining Integrator roles, updating libraries and designs and setting up project shared area.

Enabling team design

After setting up team design environment, key task is to enable team design (ETD) for a project and is done by the integrator.

When you enable a project for team design, the following happens:

• Subdesigns are assigned to team members and can be used by designers by joining the project.
• The selected design project is now in the shared area.

Joining team design as member

After the integrator has set up the shared area and assigned ownership rights for sub-designs, designers access the project and start work on the sub-designs they own.

Working with designs in team design environment – doing check-in and check-out

The TDO user interface offers tooltips and icons to help you perform various data management tasks that include check-in/check-out and doing modifications.

Click here for the Rapid Adoption Kit and for the detailed step-by-step procedures on the Team Design functionality, as well as various other aspects that are not covered in this blog.

Also watch the video on Enabling a DEHDL project for Team Design.

Note: The above link can only be accessed by Cadence customers who have valid login ID for https://support.cadence.com

Let me tell you a funny story.

We’ve been working with an outside research agency to write an eBook with new insights into ECAD data management. And based on the findings, I wanted to write a blog about how risky it is to just put your ECAD data on a network or shared drive with a file and folder structure. I thought I had a pretty solid first draft of that blog post written before going away for Christmas.

We were moving from one shared storage system to a new one. I always stored my files in a shared folder so everyone on the team could access and edit them, much like many groups manage their ECAD data today. Since I knew we were migrating systems during the holiday, I made a complete backup of my data locally and slept fine for two weeks while on vacation. 

And when I came back... Gone.

Even today, I still don't know where it went. 

Where Are Your Files, Dude?

Maybe it was the file names, perhaps my backup didn’t complete... I have no idea. But my blog article and my search ads for the eBook are gone. Trust me, the irony of losing a blog post about the risks of poorly managed data is not lost on me.

Oh well, I'll just rewrite the article and ads and have an ironic (I swear this is true, this actually happened and I'm actually redoing the work) story to tell. And believe me, I’ll be using a proper data management system instead of a network drive from now on.

A blog post, some ad copy, not really a big deal.

What if it was design data? What if it was your customer's design data? How long would it take to recreate it? How much shade would your coworkers throw your way if you deleted their data from a network drive and they had to spend the weekend recreating it? How embarrassing would it be to go back to the customer and say you lost their files and needed them again?  At best, you’re spending time on non-value add tasks in looking for and recreating missing data. At worst, you may have a customer data or security concern and you might be spending non-value add time looking for a new job.

I thought I had a pretty fool-proof folder structure and file naming convention setup. I even had a local backup. And I still lost my files. Want to know the scariest part: I don't even know what all is missing. So far, I know I've lost a blog post and some ad copy. But maybe there's more...

They're Right Here, Dude

So here we are, the week after I get back from Vacation. And I get an email from my boss. “I messed up” the subject line reads. He’d been editing a PPT on the network drive, deleted some slides he didn’t need, saved it (overwriting the original), and then realizing his mistake, proceeded to delete the whole PPT.

(Also a true story; I couldn’t make this up!)

No worries. Now that I have a data management system in place, I reverted back to the original and no one needs to know.

Download the Free eBook

Anyways, check out this eBook about ECAD data management. And please, be better about your design data than I am with my Word documents.

When it comes to choosing a design-capture tool in the EDA world, there is no one-size-fits-all solution. Depending on a variety of factors, most of all personal preferences, the answer to “Which is the best design-capture application?” keeps changing. Most design tasks can be accomplished in all tools. Some tools might even look similar.

In this scenario, what differentiates one product from the rest is highly subjective. Usability, or ease of use combined with efficiency, is a key determinant. A user might ask: 

• How much do I need to know in advance? How much do I need to figure out?
• How many clicks are needed for doing the same task?
• How well does it work with other applications in the design-to-fabrication flow?
• How easy is it to extract information for different departments?
• Does it include a robust library? Can I extend the available libraries?
• Can I reuse my designs?
• How much of it is automated?

Allegro System Design Authoring (SDA) is a powerful, enterprise-level application that addresses these concerns and brings you the robustness of Design Entry HDL and the lightness of OrCAD® Capture. SDA offers a gamut of new features and simpler, faster ways of completing design-capture tasks. Let’s take a look at the top 10 of the many features of Allegro SDA and how they benefit you, the designer:

This just begins to scratch the surface. SDA not only looks modern, it has built-in mechanisms that are contemporary and smart. Even though the interface and use models are intuitive, SDA Help includes a robust library of technical videos that quickly demonstrate SDA features and an FAQ that addresses the most common questions. When you work with SDA, your design efficiency improves, and you'll realize how the entire PCB design ecosystem gets connected and streamlined.  

The next generation of schematic entry is here.  

For more information about SDA visit:  http://support.cadence.com/wps/AllegroSDA

Using Sensitivity Analysis of PSpice

I was thinking of writing a series of blogs showcasing what all ammunition's a circuit designer may need to deal with any complex circuits today. So, here's the first one. 

When in college, books tell you everything about your circuit. You already know which components are critical in your designs. But, what about when you enter an industry? You have completely new designs that you build or come across and you need to know which components are critical for your measurement goals. The first thing a designer has to be sure of is to thoroughly understand/ know their circuit. 

In the first Tech-Blog of this series, we will take a sample RF Amplifier circuit and perform PSpice Sensitivity Analysis on it. Read more into how this Advanced Analysis capability helps you reduce circuit design costs considerably.

Continue Reading on PSpice.com